AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator

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ID 683387
Date 3/29/2021
Public
Document Table of Contents
Document Table of Contents x
1. List of Abbreviations 2. Introduction 3. Intel® Stratix® 10 FPGA Package Mechanical Design 4. Intel® Stratix® 10 FPGA Thermal Design Parameters 5. Thermal Design Process for Intel® Stratix® 10 Devices 6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices 7. Maximum Power and Typical Power 8. Document Revision History for AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator
3. Intel® Stratix® 10 FPGA Package Mechanical Design x
3.1. Intel® Stratix® 10 Physical Package Structure
4. Intel® Stratix® 10 FPGA Thermal Design Parameters x
4.1. Intel® Stratix® 10 Compact Thermal Model (CTM) 4.2. Intel® Stratix® 10 Temperature Sensing 4.3. Thermal Sensor Accuracy
6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices x
6.1. Device Selection 6.2. Logic Design Information 6.3. Thermal Settings and Parameters 6.4. Thermal Design Optimization 6.5. Updating Thermal Parameters 6.6. Intel® Stratix® 10 Device with PCIe Thermal Design Example 1 6.7. Heat Sink 6.8. Intel® Stratix® 10 Device with PCIe Thermal Design Example 2 (Alternate Method)
6.8. Intel® Stratix® 10 Device with PCIe Thermal Design Example 2 (Alternate Method) x
6.8.1. Analyzing 1U Sled with 3 FPGAs
1. List of Abbreviations
2. Introduction
3. Intel® Stratix® 10 FPGA Package Mechanical Design
4. Intel® Stratix® 10 FPGA Thermal Design Parameters
5. Thermal Design Process for Intel® Stratix® 10 Devices
6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices
7. Maximum Power and Typical Power
8. Document Revision History for AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator

5. Thermal Design Process for Intel® Stratix® 10 Devices

This topic describes the stages of the Intel® Stratix® 10 FPGA thermal design process.
Figure 5.  Thermal Design Flow

Thermal Design Stages

  1. Supply design information to the Intel® FPGA Power and Thermal Calculator (PTC). This step provides the necessary data to estimate the power dissipation of each die. The inputs include the FPGA design information as well as the thermal design requirements of TA and TJ-MAX and power margin selection. At this point the design is still in its early stages; be aware that power predictions at this point may have inaccuracies and should not be taken as indicative of the final values for a functional design.
  2. Obtain thermal design parameters. The PTC provides the thermal design parameters. The power dissipation of the transceiver die is provided as a constant value, but the main core die power dissipation is provided as a function of its junction temperature, and should be entered into the computational fluid dynamic (CFD) tool as a function of temperature for most accurate results.
  3. Obtain the compact thermal model (CTM). Contact your Intel representative to obtain the applicable CTM for the CFD analysis.
  4. Run the CFD analysis. Model the system in the CFD tool and apply all the applicable power values to the corresponding dies. The CFD solution provides the core die total thermal power (TTP) and temperature and the TCASE. The CFD cannot predict the transceiver and HBM die temperatures, therefore those must be calculated manually.
  5. Compare the CFD results with the PTC results. If the CFD values for the TCASE , or TJ of the core die are equal to or less than those calculated by the PTC, then the cooling solution is sufficient. If the TCASE , or TJ of the core die are higher than those calculated by the PTC, then additional cooling, or design changes such as transceiver placement optimization, may be needed. Use the data from the CFD analysis to calculate the TJ of each die or the effective ΨCA, using the following equations:
    In the above equations, TTP and TCASE are the CFD results. The maximum TJ is the die with the highest ΨJC reported by PTC. To calculate the TJ-MAX, use that ΨJC in the above equation.
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