AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator

Download PDF
ID 683387
Date 3/29/2021
Public
Document Table of Contents
Document Table of Contents x
1. List of Abbreviations 2. Introduction 3. Intel® Stratix® 10 FPGA Package Mechanical Design 4. Intel® Stratix® 10 FPGA Thermal Design Parameters 5. Thermal Design Process for Intel® Stratix® 10 Devices 6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices 7. Maximum Power and Typical Power 8. Document Revision History for AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator
3. Intel® Stratix® 10 FPGA Package Mechanical Design x
3.1. Intel® Stratix® 10 Physical Package Structure
4. Intel® Stratix® 10 FPGA Thermal Design Parameters x
4.1. Intel® Stratix® 10 Compact Thermal Model (CTM) 4.2. Intel® Stratix® 10 Temperature Sensing 4.3. Thermal Sensor Accuracy
6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices x
6.1. Device Selection 6.2. Logic Design Information 6.3. Thermal Settings and Parameters 6.4. Thermal Design Optimization 6.5. Updating Thermal Parameters 6.6. Intel® Stratix® 10 Device with PCIe Thermal Design Example 1 6.7. Heat Sink 6.8. Intel® Stratix® 10 Device with PCIe Thermal Design Example 2 (Alternate Method)
6.8. Intel® Stratix® 10 Device with PCIe Thermal Design Example 2 (Alternate Method) x
6.8.1. Analyzing 1U Sled with 3 FPGAs
1. List of Abbreviations
2. Introduction
3. Intel® Stratix® 10 FPGA Package Mechanical Design
4. Intel® Stratix® 10 FPGA Thermal Design Parameters
5. Thermal Design Process for Intel® Stratix® 10 Devices
6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices
7. Maximum Power and Typical Power
8. Document Revision History for AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator

4. Intel® Stratix® 10 FPGA Thermal Design Parameters

The Intel® Stratix® 10 FPGA thermal parameters do not contain the traditional θJC and θJB values, due to its MCM construction. Instead of 2R resistor values, the Intel® FPGA Power and Thermal Calculator (PTC) provides ΨJC and ΨCA values which are used with MCM packages and are highly design-dependent. Therefore, you cannot use the two resistor models for the thermal modeling of the package. Intel® offers a compact thermal model (CTM) which is discussed in the following topic. The table below lists the thermal design parameters used in this document.
Table 2.  Thermal Design Parameters
Parameter Description
TA Ambient temperature, measured locally surrounding the FPGA. Measure the ambient temperature just upstream of a passive heat sink or at the fan inlet for an active heat sink. This value affects the junction temperature of the main FPGA core fabric die and its power dissipation.
TJ-MAX The maximum rated junction temperature of a die, or could be the design goal. For example, a particular die could have a manufacturer's specified TJ-MAX of 100°C, but designers can specify a TJ-MAX of less than 100°C as part of their design requirement.
TJ The junction temperature of a die calculated by the PTC for a condition. The PTC does not report this value directly, but it can be calculated from the information provided.
Power The PTC reports the power dissipation of each die individually.
Total Thermal Power (TTP) The total power dissipation of the device. This includes static power, with static power savings subtracted. The PTC reports this value in the Power Summary window.
ΨJC The thermal resistance between each of the dies in the package and the center of the package integrated heat spreader (IHS). A multi-chip module (MCM) such as the Intel® Stratix® 10 device has as many ΨJC values as the number of dies in the package. The PTC reports the maximum ΨJC value which corresponds to the die with the highest temperature on the device. The ΨJC value is calculated by this equation:

ΨJC = (TJ - TCASE) / TTP

Note:
  1. ΨJC values are not constant for a specific package and change as the FPGA resource usage changes.
  2. Refer to the figure Individual Die Thermal Resistance to the Top of IHS, following this table, for an illustration of individual die (PSI_JC).
ΨCA The thermal resistance between the center of the package IHS and the ambient temperature. You can enter this value into the PTC as a thermal constraint, or it can be reported by the PTC as part of the thermal solution. ΨCA can be used as a figure of merit in assessing the required cooling solution for a design. For example, the lower the ΨCA value, the more aggressive cooling solution is needed. The value of ΨCA is calculated by this equation:

ΨCA = (TCASE - TA) / TTP

The thermal solver in the PTC works on three points in addition to your design. You can specify two of those points — for example, ambient temperature (TA) and maximum junction temperature (TJ-MAX), and the solver determines the third — for example, the thermal resistance from case to ambient, in degrees-per-watt (PSI-CA).

Note: ΨCA values are not constant for a specific package and change as the FPGA resource usage changes. You must recalculate this value for each design.
TCASE The temperature at the top center of the IHS. For a design to not exceed its TJ-MAX, the cooling solution must be able to maintain the TCASE temperature at or below the TCASE temperature calculated by the PTC.
Note: TCASE values are not constant for a specific package and change as the FPGA resource usage changes.
Figure 3. Individual Die Thermal Resistance to the Top of IHS
Figure 4. Thermal ResistanceThe diagram shows the thermal resistance from each die to the IHS top surface and also to the air.
Level Two Title