AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

ID 683343
Date 11/06/2017
Public
Document Table of Contents

ToD Interface Signals

The following table lists the ToD interface signals. These interface signals are only applicable to design examples with IEEE 1588v2.

Table 13.  ToD Interface Signals
Signal Direction Width Description
master_pulse_per_second output 1 Pulse per second (PPS) from master PPS module. The pulse per second output asserts for 10 ms.
start_tod_sync[] input [NUM_CHANNELS] Use this signal to trigger the TOD synchronization process. The time of day of the local TOD is synchronized to the time of day of the master TOD. The synchronization process continues as long as this signal remains asserted.
pulse_per_second_10g[] output [NUM_CHANNELS] PPS from the 10G PPS module of channel n. The signal stay asserted for 10 ms.
pulse_per_second_1g[] output [NUM_CHANNELS] PPS from the 1G PPS module of channel n. The signal stay asserted for 10 ms.