Avalon-ST Interface Signals
The following table lists the Avalon-ST interface signals. These interface signals are applicable to both design examples.
Signal | Direction | Width | Description |
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avalon_st_tx_startofpacket[] | input | [NUM_CHANNELS] | Assert this signal to mark the beginning of the transmit data on the Avalon-ST interface. |
avalon_st_tx_endofpacket[] | input | [NUM_CHANNELS] | Assert this signal to mark the end of the transmit data on the Avalon-ST interface. |
avalon_st_tx_valid[] | input | [NUM_CHANNELS] | Assert this signal to indicate that avalon_st_tx_data[] and other signals on this interface are valid. |
avalon_st_tx_ready[] | output | [NUM_CHANNELS] | When asserted, this signal indicates that the MAC IP core is ready to accept data. |
avalon_st_tx_error[][] | input | [NUM_CHANNELS][64] | Assert this signal to indicate the current transmit packet contains errors. |
avalon_st_tx_data[][] | input | [NUM_CHANNELS][3] | Carries the transmit data from the client. |
avalon_st_tx_empty[] | input | [NUM_CHANNELS] | Use this signal to specify the number of bytes that are empty (not used) during cycles that contain the end of a packet. 0x0=All bytes are valid. 0x1=The last byte is invalid. 0x2=The last two bytes are invalid. 0x3=The last three bytes are invalid. |
avalon_st_rx_startofpacket[] | output | [NUM_CHANNELS] | When asserted, this signal marks the beginning of the receive data on the Avalon-ST interface. |
avalon_st_rx_endofpacket[] | output | [NUM_CHANNELS] | When asserted, this signal marks the end of the receive data on the Avalon-ST interface. |
avalon_st_rx_valid[] | output | [NUM_CHANNELS] | When asserted, this signal indicates that avalon_st_rx_data[]and other signals on this interface are valid. |
avalon_st_rx_ready[] | input | [NUM_CHANNELS] | Assert this signal when the client is ready to accept data. |
avalon_st_rx_error[][] | output | [NUM_CHANNELS][64] | When set to 1, the respective bits indicate an error type:
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avalon_st_rx_data[][] | output | [NUM_CHANNELS][3] | Carries the receive data to the client. |
avalon_st_rx_empty[][] | output | [NUM_CHANNELS][6] | Contains the number of bytes that are empty (not used) during cycles that contain the end of a packet. |
avalon_st_tx_status_valid[] | output | [NUM_CHANNELS] | When asserted, this signal qualifies avalon_st_txstatus_data[] and avalon_st_txstatus_error[]. |
avalon_st_tx_status_data[][] | output | [NUM_CHANNELS][40] | Contains information about the transmit frame.
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avalon_st_tx_status_error[][] | output | [NUM_CHANNELS][7] | When set to 1, the respective bit indicates the following error type in the receive frame.
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avalon_st_rxstatus_valid[] | output | [NUM_CHANNELS] | When asserted, this signal qualifies avalon_st_txstatus_data[] and avalon_st_txstatus_error[]. The MAC IP core asserts this signal in the same clock cycle avalon_st_rx_endofpacket is asserted. |
avalon_st_rxstatus_data[][] | output | [NUM_CHANNELS][40] | Contains information about the transmit frame.
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avalon_st_rxstatus_error[][] | output | [NUM_CHANNELS][7] | When set to 1, the respective bit indicates the following error type in the receive frame.
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avalon_st_pause_data[][] | input | [NUM_CHANNELS][2] | Set this signal to the following values to trigger the corresponding actions.
Note: This signal only takes effect if tx_pauseframe_enable[2:1] is 00 (default)
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