AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

ID 683343
Date 11/06/2017
Public
Document Table of Contents

Changing Speed between 1G, 100M, and 10M SGMII

To enable SGMII, the software needs to write a different value to the PHY register address offset 0x1290. Set the port to 1000Base-X mode first before you select any SGMII modes.
Table 2.   Register Value for Speed Change in SGMII Mode in Intel® Arria® 10 Transceiver PHY IP
Value Description
0x01 Enable SGMII mode and force speed to 10M
0x03 Enable SGMII mode and use SGMII auto negotiation
0x05 Enable SGMII mode and force speed to 100M
0x09 Enable SGMII mode and force speed to 1G

Forcing Port 0 to SGMII 100M mode

  1. Set Port 0 to 1000Base-X: write_32 0x02_52C0 0x11
  2. Set Port 0 to SGMII 100M: write_32 0x02_5290 0x05