AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

ID 683343
Date 11/06/2017
Public
Document Table of Contents

Clock and Reset Interface Signals

The following table lists the clock and reset interface signals. These interface signals are applicable to both design examples.

Table 6.   Clock and Reset Interface Signals
Signal Direction Width Description
mm_clk input 1 Configuration clock for Avalon-MM interface. Frequency is 125 MHz.
pll_ref_clk_1g[] input [NUM_UNSHARED_CHANNELS] Reference clock for the TX PLL in 1G mode. Frequency is 125 MHz.
pll_ref_clk_10g[] input [NUM_UNSHARED_CHANNELS] Reference clock for the TX PLL in 10G mode. Frequency is 644.53125 MHz.
cdr_ref_clk_1g[] input [NUM_UNSHARED_CHANNELS] Reference clock for the RX PLL in 1G mode. Frequency is 125 MHz.
cdr_ref_clk_10g[] input [NUM_UNSHARED_CHANNELS] Reference clock for the RX PLL in 10G mode. Frequency is 644.53125 MHz.
channel_reset_n input [NUM_CHANNELS] To reset individual Ethernet channel. This does not impact the components running at multi_channel level, e.g. master TOD, master PPS and fPLLs. Asynchronous and active low signal.
master_reset_n input 1 To reset the whole design example. Asynchronous and active low signal.
xgmii_clk output [NUM_UNSHARED_CHANNELS] Clock used for single data rate (SDR) XGMII TX & RX interface in between MAC and PHY. This clock is also used for Avalon-ST interface. Frequency is 156.25MHz.
rx_recovered_clk output [NUM_CHANNELS] This is the RX clock, which is recovered from the received data.