AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

ID 683343
Date 11/06/2017
Public
Document Table of Contents

Document Revision History for Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

Table 30.  Document Revision History
Date Version Changes
November 2017 2017.11.06
  • Rebranded as Intel.
  • Added a note to the "Clocking Diagram" topic to clarify that the IOPLL input reference clock is sourcing from input clock through global clock network.
  • Updated Figures:
    • Block Diagram for Design Example without IEEE 1588v2
    • Block Diagram for Design Example with IEEE 1588v2
  • Updated "Packet Classifier Interface Signals" table: Updated the description for the tx_egress_timestamp_request_in_valid[] , tx_egress_timestamp_request_in_fingerprint[][], and tx_ingress_timestamp_format[] signals.
  • Updated "ToD Interface Signals" table: Updated the descriptions for all signals.
September 2015 2015.09.30 Added DriftAdjust and DriftAdjustRate registers to Master, 1G and 10G TOD register tables.
June 2015 2015.06.15
  • Updated supported ACDS, Modelsimm and Synopsys versions.
  • Updated Clocking scheme for design example with and without IEEE 1588v2 from tx_pma_clkout to tx_clkout.
  • Removed timing violation notification during compilation.
  • Added note about upgrading older design example versions is not supported.
  • Added foot note Master TOD, 1G TOD and 10G TOD register maps about the default value for 'Period'.
  • Updated the steps in 'Setting Up the Design Examples' by combining unzip and setting directory steps.
  • Updated 'Channel 0 MAC RX Statistic Counter' by correcting number of packets from 28 to 12.
  • Updated sampling clock for 10G and 1G TOD from 31.75MHz and 126.98MHz to 31.746031MHz and 126.984125MHz respectively.
  • Updated 'Reset scheme at altera_eth_channel' and 'Reset scheme at altera_eth_channel_1588' figures from '~phy_rx_block_lock ~phy_led_link' to '~phy_rx_block_lock & ~phy_led_link'.
  • Updated tx_frame_maxlength and tx_frame_maxlength hardware reset value to hexadecimal value.
January 2015 2015.01.22 Updated supported ACDS release for software simulation.
December 2014 2014.12.29
  • Updated supported ACDS release for simulation.
  • Added tested ACDS release version for hardware simulation.
  • Added timing violation notification during compilation.
  • Updated clocking diagram for both design example with and without IEEE 1588v2.
  • Replaced CMU PLL to fractional PLL for entire document.
May 2014 2014.05.29 Initial release.