AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

ID 683343
Date 11/06/2017
Public
Document Table of Contents

Clocking Diagram

The following diagrams show the clocking scheme for the design example without IEEE 1588v2 and design example with IEEE 1588v2 respectively.

Figure 7. Clocking Scheme for the Design Example without IEEE 1588v2
Note: The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitter to the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design.


Figure 8. Clocking Scheme for the Design Example with IEEE 1588v2
Note: The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitter to the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design.