Visible to Intel only — GUID: bhc1410499899778
Ixiasoft
PHY Interface Signals
The following table lists the PHY interface signals. These interface signals are applicable to both design examples.
Signal | Direction | Width | Description |
---|---|---|---|
rx_serial_data[] | input | [NUM_CHANNELS] | RX serial input data |
tx_serial_data[] | output | [NUM_CHANNELS] | TX serial output data |
ethernet_1g_an[] | output | [NUM_CHANNELS] | Clause 37 Auto-Negotiation status. The PCS function asserts this signal when auto-negotiation completes. |
ethernet_1g_char_err[] | output | [NUM_CHANNELS] | 10-bit character error |
ethernet_1g_disp_err[] | output | [NUM_CHANNELS] | Disparity error signal indicating a 10-bit running disparity error. |
channel_ready[] | output | [NUM_CHANNELS] | This signal is asserted when the channel is ready for data transmission. |