Visible to Intel only — GUID: bhc1410499860784
Ixiasoft
Sync-E Support
To support Sync-E implementation, separate refclk signals to RX PLL and TX PLL and expose them at design example. The following diagrams show the signals per channel for design example without IEEE 1588v2 and design example with IEEE 1588v2 respectively.
Signals from PHY to Support Sync-E Implementation for Design Example without IEEE 1588v2
Signals from PHY to Support Sync-E Implementation for Design Example with IEEE 1588v2