AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

ID 683343
Date 11/06/2017
Public
Document Table of Contents

Sync-E Support

To support Sync-E implementation, separate refclk signals to RX PLL and TX PLL and expose them at design example. The following diagrams show the signals per channel for design example without IEEE 1588v2 and design example with IEEE 1588v2 respectively.

Signals from PHY to Support Sync-E Implementation for Design Example without IEEE 1588v2


Signals from PHY to Support Sync-E Implementation for Design Example with IEEE 1588v2