Visible to Intel only — GUID: bhc1410499894874
Ixiasoft
Avalon-MM Interface Signals
The following table lists the Avalon-MM interface signals. These interface signals are applicable to both design examples.
Signal | Direction | Width | Description |
---|---|---|---|
write | input | 1 | Assert this signal to request a write. |
read | input | 1 | Assert this signal to request a read. |
address[] | input | 20 | Use this bus to specify the register address you want to read from or write to. |
writedata[] | input | 32 | Carries the data to be written to the specified register. |
readdata[] | output | 32 | Carries the data read from the specified register. |
waitrequest | output | 1 | When asserted, this signal indicates that the IP core is busy and not ready to accept any read or write requests. |