Visible to Intel only — GUID: bhc1410499911115
Ixiasoft
Master TOD
Master TOD registers are applicable only to design examples with IEEE 1588v2.
The base address of the Master ToD registers are defined as follows:
- Master TOD Base Address = MSA0 + 0x01_0000
Byte Offset | R/W | Name | Description | HW Reset |
---|---|---|---|---|
0x0000 | RW | SecondsH |
|
0x0 |
0x0004 | RW | SecondsL | Bits 0 to 32: Low-order 32-bit second field. | 0x0 |
0x0008 | RW | NanoSec | Bits 0 to 32: 32-bit nanosecond field. | 0x0 |
0x0010 | RW | Period |
|
N |
0x0014 | RW | AdjustPeriod | The period for the offset adjustment.
|
0x0 |
0x0018 | RW | AdjustCount |
|
0x0 |
0x001C | RW | DriftAdjust | The drift of ToD adjusted periodically by adding a correction value as configured in this register space.
|
0x0 |
0x0020 | RW | DriftAdjustRate | The count of clock cycles for each ToD’s drift adjustment to take effect.
|
0x0 |