AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

ID 683343
Date 11/06/2017
Public
Document Table of Contents

Master TOD

Master TOD registers are applicable only to design examples with IEEE 1588v2.

The base address of the Master ToD registers are defined as follows:

  • Master TOD Base Address = MSA0 + 0x01_0000
Table 16.   Register Description and Address Offset for 1588 TOD Clock
Byte Offset R/W Name Description HW Reset
0x0000 RW SecondsH
  • Bits 0 to 15: High-order 16-bit second field
  • Bits 16 to 31: Not used.
0x0
0x0004 RW SecondsL Bits 0 to 32: Low-order 32-bit second field. 0x0
0x0008 RW NanoSec Bits 0 to 32: 32-bit nanosecond field. 0x0
0x0010 RW Period
  • Bits 0 to 15: Period in fractional nanosecond
  • Bits 16 to 19: Period in nanosecond
  • Bits 20 to 31: Not used.
N
0x0014 RW AdjustPeriod The period for the offset adjustment.
  • Bits 0 to 15: Period in fractional nanosecond
  • Bits 16 to 19: Period in nanosecond
  • Bits 20 to 31: Not used.
0x0
0x0018 RW AdjustCount
  • Bits 0 to 19: The number of AdjustPeriod clock cycles used during offset adjustment
  • Bits 20 to 31: Not used.
0x0
0x001C RW DriftAdjust The drift of ToD adjusted periodically by adding a correction value as configured in this register space.
  • Bits 0 to 15: Adjustment value in fractional nanosecond (DRIFT_ADJUST_FNS). This value is added into the current ToD during the adjustment.
  • Bits 16 to 19: Adjustment value in nanosecond (DRIFT_ADJUST_NS). This value is added into the current ToD during the adjustment.
  • Bits 20 to 32: Not used.
0x0
0x0020 RW DriftAdjustRate The count of clock cycles for each ToD’s drift adjustment to take effect.
  • Bits 0 to 15: The number of clock cycles (ADJUST_RATE). The ToD adjustment happens once after every period in number of clock cycles as indicated by this register space.
  • Bits 20 to 32: Not used.
0x0