Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 5/23/2024
Public
Document Table of Contents

2.3. Functional Description

The Stratix® 10 H-tile and L-tile design examples consist of various components. The following block diagrams show the design components and the top level connections of the design examples.

Figure 7. Design Example for Simplex Core in Standard Clocking Mode
Figure 8. Design Example for Duplex Core in Standard Clocking Mode