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1. Quick Start Guide
2. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example
3. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
4. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example
5. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
6. Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide Archives
7. Document Revision History for Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide
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Ixiasoft
5. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
This design example demonstrates the functionality of data streaming using advanced clocking mode.
To generate the design example, select any of the following presets:
- Advanced Clocking Mode 4x28.0G
- Advanced Clocking Mode 2x25.0G
- Advanced Clocking Mode 6x12.5G
- Advanced Clocking Mode 6x17.4G
The design examples are available only in duplex mode.
Note: To target the Stratix® 10 E-tile device with the Stratix® 10 TX Signal Integrity development kit, make sure to select E-Tile for the Transceiver Tile parameter in the IP tab.