Visible to Intel only — GUID: xzm1475738146979
Ixiasoft
1. Quick Start Guide
2. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example
3. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
4. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example
5. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
6. Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide Archives
7. Document Revision History for Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide
Visible to Intel only — GUID: xzm1475738146979
Ixiasoft
2.3.3. Clocking Scheme
The following diagrams show the clocking scheme for the design example.
Figure 12. Clocking Scheme for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Simplex Core in Standard Clocking Mode
Figure 13. Clocking Scheme for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Duplex Core in Standard Clocking Mode