Visible to Intel only — GUID: oqq1475828465930
Ixiasoft
Visible to Intel only — GUID: oqq1475828465930
Ixiasoft
3.6. Signals
Signal | Direction | Width | Description |
---|---|---|---|
Clock and Reset Signal | |||
mgmt_clk | Input | 1 |
Input clock for:
|
pll_ref_clk | Input | 1 | This reference clock is used by the Clock Data Recovery (CDR) unit in the transceiver. It serves as a reference for the CDR to recover the clock from the serial line. The frequency of this clock must match the frequency you select in the IP parameter editor. It should also match the frequency of the tx_pll_ref_clk reference clock for the TX PLL at the Source variant. |
mgmt_reset_n | Input | 1 | Design example asynchronous master reset. Assert this reset signal to reset the overall design example system. This is an active low signal. |
snk_core_reset_n | Output | 1 | Demo management module asserts this signal to reset traffic checker module. |
src_core_reset_n | Output | 1 | Demo management module asserts this signal to reset traffic generator module. |
Data Signal | |||
rx[n] | Input | Based on Number of Lanes value | This vector carries the transmitted streaming data from the core. n represents the number of lanes. |
tx[n] | Output | Based on Number of Lanes value | This vector carries the transmitted streaming data to the core. n represents the number of lanes. |
Status Signal | |||
rx_activity_n | Output | 1 | This single bit signal indicates that the data is valid. |
tx_activity_n | Output | 1 | This single bit signal indicates that the data is valid. |
snk_link_up_n | Output | 1 | The core asserts this signal to indicate that the core initialization is complete and is ready to receive user data. |
src_link_up_n | Output | 1 | The core asserts this signal to indicate that the core initialization is complete and is ready to transmit user data. |