Visible to Intel only — GUID: lkf1485415027693
Ixiasoft
1. Quick Start Guide
2. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example
3. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
4. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example
5. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
6. Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide Archives
7. Document Revision History for Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide
Visible to Intel only — GUID: lkf1485415027693
Ixiasoft
1.3.1. Procedure
This is a general procedure on how to generate the design example.
To generate the design example from the IP parameter editor:
- In the IP Catalog (Tools > IP Catalog), locate and select Serial Lite III Streaming. The IP parameter editor appears.
- Specify a top-level name and the folder for your custom IP variation. Click OK.
- Select a design from the Presets library and click Apply. When you select a design, the system automatically populates the IP parameters for the design.
Note: If you select another design, the settings of the IP parameters change accordingly.
- Specify the parameters for your design.
- Click the Generate Example Design button.
The software generates all design files in the sub-directories. These files are required to run simulation, compilation, and hardware testing.