Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 5/23/2024
Public
Document Table of Contents

2.3.1. Design Example Components

The design example consists of the following components:

  • Serial Lite III Streaming IP core variation
  • Source and sink user clock—fPLL
  • ATX PLL
  • Traffic generator
  • Traffic checker
  • Demo control
  • Demo management