Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 5/23/2024
Public
Document Table of Contents

2.3.2. Reset Scheme

The mgmt_reset_n reset signal controls the overall reset structure for the design example. This is an asynchronous and active-low signal. Asserting this signal resets the demo control module and the Serial Lite III Streaming IP core. The traffic generator and traffic checker modules get reset through the demo management and the reset synchronizer.

The following diagrams show the reset scheme implemented in the design example.
Figure 10. Reset Scheme for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Simplex Core in Standard Clocking Mode
Figure 11. Reset Scheme for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Duplex Core in Standard Clocking Mode