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1. Quick Start Guide
2. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example
3. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
4. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example
5. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
6. Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide Archives
7. Document Revision History for Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide
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Ixiasoft
5.3.1.5. Demo Control
The demo control module is a Nios® V processor system, generated in Platform Designer (Standard), to control the demo hardware.
Demo control module also consists of a timer to track interrupt occurrence, Avalon® memory-mapped interface to access demo management and the Serial Lite III Streaming Intel® FPGA IP PHY interface, a reset controller, a UART interface, and an Avalon® streaming interface.