Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 5/23/2024
Public
Document Table of Contents

7. Document Revision History for Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.05.23 24.1 20.1.0 Updated Nios II to Nios® V
2021.11.01 21.3 19.3.0
  • Removed mentions of NCSim support throughout the document:
  • Added support for QuestaSim* simulator.
2020.06.16 18.1 18.1
  • Clarified the following in the Compiling and Testing the Design topic:
    • H-tile and L-tile design examples use the Stratix® 10 GX development kit
    • E-tile design examples target the Stratix® 10 TX Signal Integrity development kit
    • users must generate remap the pins to match the Stratix® 10 TX Signal Integrity development kit to use H-tile design examples in the Stratix® 10 TX Signal Integrity development kit.
  • Added note to clarify users must generate remap the pins to match the Stratix® 10 TX Signal Integrity development kit to use H-tile design examples in the Stratix® 10 TX Signal Integrity development kit in Hardware and Software Requirements topic for H-tile and L-tile standard and advanced clocking mode design examples.
2018.12.28 18.1 18.1
  • Renamed the IP core to Serial Lite III Streaming Intel® FPGA IP.
  • Renamed the document to SerialLite III Streaming Stratix® 10 FPGA IP Design Example User Guide.
  • Added design example presets for Stratix® 10 E-tile devices:
    • Standard and Advanced Clocking Mode 2x25.0G
    • Standard and Advanced Clocking Mode 4x28.0G
    • Standard and Advanced Clocking Mode 6x12.5G
    • Standard and Advanced Clocking Mode 6x17.4G
  • Added new sections for the Stratix® 10 E-tile Standard and Advanced Clocking Mode design examples.
  • Added new design example presets for Stratix® 10 H-tile and L-tile devices:
    • Standard and Advanced Clocking Mode 2x25.0G
    • Standard and Advanced Clocking Mode 4x28.0G
  • Added simplex mode support for Stratix® 10 H-tile and L-tile design examples. Stratix® 10 E-tile design examples support only duplex mode.
  • Added simplex mode block diagrams for the Stratix® 10 H-tile and L-tile design examples.
  • Added an example of a successful simulation in the Simulation sections and examples of successful tests in the Hardware Testing sections.
  • Updated the Error Details section to include source error about adaptation FIFO overflow.
  • Updated the Parameter Settings for Stratix® 10 Design Example Standard and Advanced Clocking Presets tables with E-tile information.
Date Version Changes
November 2017 2017.11.06
  • Rebranded as Intel.
  • Renamed the document as SerialLite III Streaming IP Core Design Example User Guide for Intel Stratix 10 Devices.
  • Updated the "Parameters in the Example Design Tab" table: Updated the descriptions for Select Board parameter.
May 2017 2017.05.08
  • Initial release.