Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide

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ID 683341
Date 5/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example 3. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example 4. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example 5. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example 6. Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide Archives 7. Document Revision History for Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Example Block Diagrams 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design
1.3. Generating the Design x
1.3.1. Procedure 1.3.2. Design Example Parameters 1.3.3. Presets
1.4. Simulating the Design x
1.4.1. Procedure
2. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Signals
2.3. Functional Description x
2.3.1. Design Example Components 2.3.2. Reset Scheme 2.3.3. Clocking Scheme
2.3.1. Design Example Components x
2.3.1.1. Serial Lite III Streaming IP Core 2.3.1.2. User Clock 2.3.1.3. Traffic Generator 2.3.1.4. Traffic Checker 2.3.1.5. Demo Control 2.3.1.6. Demo Management 2.3.1.7. Nios® V Processor Code
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Design Setup 2.5.2. Error Details
3. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Signals
3.3. Functional Description x
3.3.1. Design Example Components 3.3.2. Reset Scheme 3.3.3. Clocking Scheme
3.3.1. Design Example Components x
3.3.1.1. Serial Lite III Streaming IP Core 3.3.1.2. User Clock 3.3.1.3. Traffic Generator 3.3.1.4. Traffic Checker 3.3.1.5. Demo Control 3.3.1.6. Demo Management 3.3.1.7. Nios® V Processor Code
3.4. Simulation x
3.4.1. Testbench
3.5. Hardware Testing x
3.5.1. Design Setup 3.5.2. Error Details
4. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Hardware Testing 4.6. Signals
4.3. Functional Description x
4.3.1. Design Example Components 4.3.2. Reset Scheme 4.3.3. Clocking Scheme
4.3.1. Design Example Components x
4.3.1.1. Serial Lite III Streaming IP Core 4.3.1.2. User Clock 4.3.1.3. Traffic Generator 4.3.1.4. Traffic Checker 4.3.1.5. Demo Control 4.3.1.6. Demo Management 4.3.1.7. Nios® V Processor Code
4.4. Simulation x
4.4.1. Testbench
4.5. Hardware Testing x
4.5.1. Design Setup 4.5.2. Error Details
5. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Hardware Testing 5.6. Signals
5.3. Functional Description x
5.3.1. Design Example Components 5.3.2. Reset Scheme 5.3.3. Clocking Scheme
5.3.1. Design Example Components x
5.3.1.1. Serial Lite III Streaming IP Core 5.3.1.2. User Clock 5.3.1.3. Traffic Generator 5.3.1.4. Traffic Checker 5.3.1.5. Demo Control 5.3.1.6. Demo Management 5.3.1.7. Nios® V Processor Code
5.4. Simulation x
5.4.1. Testbench
5.5. Hardware Testing x
5.5.1. Design Setup 5.5.2. Error Details
1. Quick Start Guide
2. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example
3. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
4. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example
5. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
6. Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide Archives
7. Document Revision History for Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide

7. Document Revision History for Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.05.23 24.1 20.1.0 Updated Nios II to Nios® V
2021.11.01 21.3 19.3.0
  • Removed mentions of NCSim support throughout the document:
  • Added support for QuestaSim* simulator.
2020.06.16 18.1 18.1
  • Clarified the following in the Compiling and Testing the Design topic:
    • H-tile and L-tile design examples use the Stratix® 10 GX development kit
    • E-tile design examples target the Stratix® 10 TX Signal Integrity development kit
    • users must generate remap the pins to match the Stratix® 10 TX Signal Integrity development kit to use H-tile design examples in the Stratix® 10 TX Signal Integrity development kit.
  • Added note to clarify users must generate remap the pins to match the Stratix® 10 TX Signal Integrity development kit to use H-tile design examples in the Stratix® 10 TX Signal Integrity development kit in Hardware and Software Requirements topic for H-tile and L-tile standard and advanced clocking mode design examples.
2018.12.28 18.1 18.1
  • Renamed the IP core to Serial Lite III Streaming Intel® FPGA IP.
  • Renamed the document to SerialLite III Streaming Stratix® 10 FPGA IP Design Example User Guide.
  • Added design example presets for Stratix® 10 E-tile devices:
    • Standard and Advanced Clocking Mode 2x25.0G
    • Standard and Advanced Clocking Mode 4x28.0G
    • Standard and Advanced Clocking Mode 6x12.5G
    • Standard and Advanced Clocking Mode 6x17.4G
  • Added new sections for the Stratix® 10 E-tile Standard and Advanced Clocking Mode design examples.
  • Added new design example presets for Stratix® 10 H-tile and L-tile devices:
    • Standard and Advanced Clocking Mode 2x25.0G
    • Standard and Advanced Clocking Mode 4x28.0G
  • Added simplex mode support for Stratix® 10 H-tile and L-tile design examples. Stratix® 10 E-tile design examples support only duplex mode.
  • Added simplex mode block diagrams for the Stratix® 10 H-tile and L-tile design examples.
  • Added an example of a successful simulation in the Simulation sections and examples of successful tests in the Hardware Testing sections.
  • Updated the Error Details section to include source error about adaptation FIFO overflow.
  • Updated the Parameter Settings for Stratix® 10 Design Example Standard and Advanced Clocking Presets tables with E-tile information.
Date Version Changes
November 2017 2017.11.06
  • Rebranded as Intel.
  • Renamed the document as SerialLite III Streaming IP Core Design Example User Guide for Intel Stratix 10 Devices.
  • Updated the "Parameters in the Example Design Tab" table: Updated the descriptions for Select Board parameter.
May 2017 2017.05.08
  • Initial release.
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