Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide

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ID 683341
Date 5/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example 3. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example 4. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example 5. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example 6. Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide Archives 7. Document Revision History for Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Example Block Diagrams 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design
1.3. Generating the Design x
1.3.1. Procedure 1.3.2. Design Example Parameters 1.3.3. Presets
1.4. Simulating the Design x
1.4.1. Procedure
2. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Signals
2.3. Functional Description x
2.3.1. Design Example Components 2.3.2. Reset Scheme 2.3.3. Clocking Scheme
2.3.1. Design Example Components x
2.3.1.1. Serial Lite III Streaming IP Core 2.3.1.2. User Clock 2.3.1.3. Traffic Generator 2.3.1.4. Traffic Checker 2.3.1.5. Demo Control 2.3.1.6. Demo Management 2.3.1.7. Nios® V Processor Code
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Design Setup 2.5.2. Error Details
3. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Signals
3.3. Functional Description x
3.3.1. Design Example Components 3.3.2. Reset Scheme 3.3.3. Clocking Scheme
3.3.1. Design Example Components x
3.3.1.1. Serial Lite III Streaming IP Core 3.3.1.2. User Clock 3.3.1.3. Traffic Generator 3.3.1.4. Traffic Checker 3.3.1.5. Demo Control 3.3.1.6. Demo Management 3.3.1.7. Nios® V Processor Code
3.4. Simulation x
3.4.1. Testbench
3.5. Hardware Testing x
3.5.1. Design Setup 3.5.2. Error Details
4. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Hardware Testing 4.6. Signals
4.3. Functional Description x
4.3.1. Design Example Components 4.3.2. Reset Scheme 4.3.3. Clocking Scheme
4.3.1. Design Example Components x
4.3.1.1. Serial Lite III Streaming IP Core 4.3.1.2. User Clock 4.3.1.3. Traffic Generator 4.3.1.4. Traffic Checker 4.3.1.5. Demo Control 4.3.1.6. Demo Management 4.3.1.7. Nios® V Processor Code
4.4. Simulation x
4.4.1. Testbench
4.5. Hardware Testing x
4.5.1. Design Setup 4.5.2. Error Details
5. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Hardware Testing 5.6. Signals
5.3. Functional Description x
5.3.1. Design Example Components 5.3.2. Reset Scheme 5.3.3. Clocking Scheme
5.3.1. Design Example Components x
5.3.1.1. Serial Lite III Streaming IP Core 5.3.1.2. User Clock 5.3.1.3. Traffic Generator 5.3.1.4. Traffic Checker 5.3.1.5. Demo Control 5.3.1.6. Demo Management 5.3.1.7. Nios® V Processor Code
5.4. Simulation x
5.4.1. Testbench
5.5. Hardware Testing x
5.5.1. Design Setup 5.5.2. Error Details
1. Quick Start Guide
2. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example
3. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
4. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example
5. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
6. Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide Archives
7. Document Revision History for Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide

1.3.3. Presets

Standard presets allow instant entry of pre-selected parameter values in the IP and Example Design tabs. You can select the presets at the lower right window in the parameter editor.

The parameter values chosen for the presets belong to the group of supported Serial Lite III Streaming IP configurations for design example generation. You can select one of the presets available for your target device to quickly generate a design example without having to manually set each parameter in the IP tab and verifying that the parameter matches the supported configurations set. There are eight preset settings available in the library that support Duplex, Sink and Source modes:

  • Standard Clocking Mode 6x12.5G
  • Standard Clocking Mode 6x17.4G
  • Standard Clocking Mode 2x25G
  • Standard Clocking Mode 4x28G
  • Advanced Clocking Mode 6x12.5G
  • Advanced Clocking Mode 6x17.4G
  • Advanced Clocking Mode 2x25G
  • Advanced Clocking Mode 4x28G
Note: Serial Lite III Streaming Intel® FPGA IP design examples for Stratix® 10 devices are only available in Quartus® Prime Pro Edition.
Table 3.  Parameter Settings for Stratix® 10 Design Example Standard Clocking Presets
Presets Standard Clocking Mode 6x12.5G Standard Clocking Mode 6x17.4G Standard Clocking Mode 2x25G Standard Clocking Mode 4x28G
Direction
  • Simplex and Duplex (H-tile and L-tile)
  • Duplex (E-tile)
  • Simplex and Duplex (H-tile and L-tile)
  • Duplex (E-tile)
  • Simplex and Duplex (H-tile and L-tile)
  • Duplex (E-tile)
  • Simplex and Duplex (H-tile and L-tile)
  • Duplex (E-tile)
Number of lanes 6 6 2 4
Meta frame length in words 200 200 200 200
Transceiver reference clock frequency (MHz) 312.5 600.0 312.5 200.0
Enable M20K ECC support ON/OFF

The default value is OFF.

ON/OFF

The default value is OFF.

ON/OFF

The default value is OFF.

ON/OFF

The default value is OFF.

Clocking Mode Standard clocking mode Standard clocking mode Standard clocking mode Standard clocking mode
Required user clock frequency (MHz) 177.556818 247.159091 355.113636 397.727273
Transceiver data rate (Gbps) 12.5 17.4 25.0 28.0
Streaming Mode Full Full Full Full
VCCR_GXB and VCCT_GXB supply voltage for the transceiver 1.0 V (applicable only for L-tile and H-tile devices) 1.0 V (applicable only for L-tile and H-tile devices) 1.1 (applicable only for L-tile and H-tile devices) 1.1 (applicable only for L-tile and H-tile devices)
Transceiver Channel Type GX (applicable only for L-tile and H-tile devices) GX (applicable only for L-tile and H-tile devices) GXT (applicable only for L-tile and H-tile devices) GXT (applicable only for L-tile and H-tile devices)
Transceiver Tile L-tile, H-tile, and E-tile devices L-tile, H-tile, and E-tile devices L-tile, H-tile, and E-tile devices L-tile, H-tile, and E-tile devices
Table 4.  Parameter Settings for Stratix® 10 Design Example Advanced Clocking Presets
Presets Advanced Clocking Mode 6x12.5G Advanced Clocking Mode 6x17.4G Advanced Clocking Mode 2x25G Advanced Clocking Mode 4x28G
Direction
  • Simplex and Duplex (H-tile and L-tile)
  • Duplex (E-tile)
  • Simplex and Duplex (H-tile and L-tile)
  • Duplex (E-tile)
  • Simplex and Duplex (H-tile and L-tile)
  • Duplex (E-tile)
  • Simplex and Duplex (H-tile and L-tile)
  • Duplex (E-tile)
Number of lanes 6 6 2 4
Meta frame length in words 200 200 200 200
Transceiver reference clock frequency (MHz) 312.5 600.0 312.5 200.0
Enable M20K ECC support ON/OFF

The default value is OFF.

ON/OFF

The default value is OFF.

ON/OFF

The default value is OFF.

ON/OFF

The default value is OFF.

Clocking Mode Advanced clocking mode Advanced clocking mode Advanced clocking mode Advanced clocking mode
Required user clock frequency (MHz)

182.835821

 254.507463 365.671642 409.552239
Transceiver data rate (Gbps) 12.5 17.4 25.0 28.0
Streaming Mode Full Full Full Full
VCCR_GXB and VCCT_GXB supply voltage for the transceiver 1.0 V (applicable only for L-tile and H-tile devices) 1.0 V (applicable only for L-tile and H-tile devices) 1.1 (applicable only for L-tile and H-tile devices) 1.1 (applicable only for L-tile and H-tile devices)
Transceiver Channel Type GX (applicable only for L-tile and H-tile devices) GX (applicable only for L-tile and H-tile devices) GXT (applicable only for L-tile and H-tile devices) GXT (applicable only for L-tile and H-tile devices)
Transceiver Tile L-tile, H-tile, and E-tile devices L-tile, H-tile, and E-tile devices L-tile, H-tile, and E-tile devices L-tile, H-tile, and E-tile devices
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