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1. Quick Start Guide
2. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example
3. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
4. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example
5. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
6. Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide Archives
7. Document Revision History for Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide
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Ixiasoft
4.5.2. Error Details
These are the list of errors reported when you run the design example.
Error | Description |
---|---|
Source Error: | |
Adaptation FIFO Overflow | To indicate source adaptation FIFO overflow error. |
Sink Errors: | |
Loss of Alignment During Normal Operation | To indicate loss of alignment error (error_rx[1]). |
Meta Frame CRC Errors | To indicate CRC errors. |
Lane Swap Errors | To indicate lane swap errors in traffic checker. |
Lane Sequence Errors | To indicate lane sequence error in traffic checker. |
Lane Alignment Errors | To indicate lane alignment error in traffic checker. |