JESD204B Intel® FPGA IP Design Example User Guide: Quartus® Prime Standard Edition

ID 683094
Date 7/19/2024
Public
Document Table of Contents

1.6.2. System Parameters

Table 30.  System Parameter SettingsThis table lists the parameters exposed at the system level.
Parameter Value 14 Default Description
LINK 1, 2 1 Number of JESD204B link. One link represent one JESD204B instance.
L 1, 2, 4, 8 2 Number of lanes per converter device.
M 1, 2, 4, 8 2 Number of converters per device.
F 1, 2, 4, 8 2 Number of octets per frame.
S 1, 2 1 Number of transmitted samples per converter per frame.
N 12–16 16 Number of conversion bits per converter.
N' 16 16 Number of transmitted bits per sample in the user data format.
F1_FRAMECLK_DIV 1, 4 4 The divider ratio on frame_clk when F = 1. The transport layer uses the post-divided frame_clk.
F2_FRAMECLK_DIV 1, 2 2 The divider ratio on frame_clk when F = 2. The transport layer uses the post-divided frame_clk.
POLYNOMIAL_LENGTH 7, 9, 15, 23, 31 7 Defines the polynomial length for the PRBS pattern generator and checker, which is also the equivalent number of stages for the shift register.
  • If PRBS-7 is required, set this parameter to 7.
  • If PRBS-9 is required, set this parameter to 9.
  • If PRBS-15 is required, set this parameter to 15.
  • If PRBS-23 is required, set this parameter to 23.
  • If PRBS-31 is required, set this parameter to 31.
This parameter value must not be larger than N, which is the output data width of the PRBS pattern generator or converter resolution. If an N of 12-14 is required, PRBS-7 and PRBS-9 are the only feasible options. If an N of 15-16 is required, PRBS-7, PRBS-9, and PRBS-15 are the only feasible options.
FEEDBACK_TAP 6, 5, 14, 18, 28 6 Defines the feedback tap for the PRBS pattern generator and checker. This is an intermediate stage that is XOR-ed with the last stage to generate to next PRBS bit.
  • If PRBS-7 is required, set this parameter to 6.
  • If PRBS-9 is required, set this parameter to 5.
  • If PRBS-15 is required, set this parameter to 14.
  • If PRBS-23 is required, set this parameter to 18.
  • If PRBS-31 is required, set this parameter to 28.

The table below lists the configuration that this design example supports. However, the design example generated by the Platform Designer (Standard) system is always fixed at a data rate of 6144 Mbps and a limited set of configuration as shown in the table below. If your setting in the Platform Designer (Standard) parameter editor does not match one of the LMF and bonded mode parameter values in the following table, the design example is generated with the default values of LMF = 124.

Table 31.  Static and Dynamic Reconfiguration Parameter Values Supported
Mode Link L M F Reference Clock Frame Clock Link Clock F1_FRAMECLK_DIV F2_FRAMECLK_DIV
Static
Bonded/Non-bonded 1 1 1 4 153.6 153.6 153.6 1
Bonded/Non-bonded 1 1 1 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 1 2 4 153.6 153.6 153.6 1
Bonded/Non-bonded 1 1 2 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 1 4 8 153.6 76.8 153.6 1
Bonded/Non-bonded 1 2 1 1 153.6 153.6 153.6 4
Bonded/Non-bonded 1 2 1 2 153.6 153.6 153.6 2
Bonded/Non-bonded 1 2 1 4 153.6 153.6 153.6 1
Bonded/Non-bonded 1 2 1 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 2 2 4 153.6 153.6 153.6 1
Bonded/Non-bonded 1 2 2 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 2 4 4 153.6 153.6 153.6 1
Bonded/Non-bonded 1 2 4 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 2 8 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 4 1 1 153.6 153.6 153.6 4  
Bonded/Non-bonded 1 4 1 2 153.6 153.6 153.6 2
Bonded/Non-bonded 1 4 1 4 153.6 153.6 153.6 1  
Bonded/Non-bonded 1 4 2 1 153.6 153.6 153.6 4
Bonded/Non-bonded 1 4 2 2 153.6 153.6 153.6 2
Bonded/Non-bonded 1 4 2 4 153.6 153.6 153.6 1  
Bonded/Non-bonded 1 4 2 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 4 4 2 153.6 153.6 153.6 2
Bonded/Non-bonded 1 4 4 4 153.6 153.6 153.6 1
Bonded/Non-bonded 1 4 4 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 4 8 4 153.6 153.6 153.6 1
Bonded/Non-bonded 1 4 8 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 4 16 8 153.6 76.8 153.6 1  
Bonded/Non-bonded 1 8 1 1 307.2 153.6 153.6 4
Bonded/Non-bonded 1 8 1 2 307.2 153.6 153.6 2
Bonded/Non-bonded 1 8 2 1 307.2 153.6 153.6 4
Bonded/Non-bonded 1 8 2 2 307.2 153.6 153.6 2
Bonded/Non-bonded 1 8 2 4 307.2 153.6 153.6 1  
Bonded/Non-bonded 1 8 4 1 307.2 153.6 153.6 4
Bonded/Non-bonded 1 8 4 2 307.2 153.6 153.6 2
Bonded/Non-bonded 1 8 4 4 307.2 153.6 153.6 1  
Bonded/Non-bonded 1 8 4 8 307.2 76.8 153.6 1  
Bonded/Non-bonded 1 8 8 2 307.2 153.6 153.6 2
Bonded/Non-bonded 1 8 8 4 307.2 153.6 153.6 1  
Bonded/Non-bonded 1 8 8 8 307.2 76.8 153.6 1  
Bonded/Non-bonded 1 8 16 4 307.2 153.6 153.6 1  
Bonded/Non-bonded 1 8 16 8 307.2 76.8 153.6 1  
Bonded/Non-bonded 1 8 32 8 307.2 76.8 153.6 1
Bonded/Non-bonded 2 1 1 2 153.6 153.6 153.6 2
Bonded/Non-bonded 2 2 2 2 153.6 153.6 153.6 2
Dynamic Reconfiguration
Non-bonded 2 2 2 2 153.6 153.6 153.6 2
The following figures show the datapath of single and multiple JESD204B links.
Figure 20.  Datapath of A Single JESD204B Link


Figure 21.  Datapath of Multiple JESD204B Links


14 Values supported or demonstrated by this design example.