JESD204B Intel® FPGA IP Design Example User Guide: Quartus® Prime Standard Edition

ID 683094
Date 7/19/2024
Public
Document Table of Contents

1.6.4.1. Dynamic Reconfiguration Operation

The dynamic reconfiguration feature implements various reconfiguration controller modules such as PLL reconfiguration, Transceiver Reconfiguration Controller, SPI master, and JESD204B IP core Avalon-MM slave. These modules connect to the control unit through the Avalon-MM interface. You can control the reconfiguration using the reconfig, runtime_lmf, and runtime_datarate input ports exposed at control unit interface.

Figure 22. Dynamic Reconfiguration Block Diagram (For 28 nm Device Families—Stratix V and Arria V)


Figure 23. Dynamic Reconfiguration Block Diagram (For 20 nm Device Families—Arria 10)


The MIF ROM content for maximum and downscale configuration:

  • PLL MIF ROM—contains the PLL counter, charge pump, and bandwidth setting.
  • JESD MIF ROM—contains the LMF information.
  • PHY MIF ROM—contains the transceiver channel and PLL setting.
  • ADC MIF ROM—contains the ADC converter setting.
  • DAC MIF ROM—contains the DAC converter setting.
  • CLK MIF ROM—contains the device clock setting.