JESD204B Intel® FPGA IP Design Example User Guide: Quartus® Prime Standard Edition

ID 683094
Date 7/19/2024
Public
Document Table of Contents

1.6.1.7.2. Data Bit and Content Mapping Scheme

One major function of the transport layer is to arrange the data bits in a specific way between the Avalon-ST interface and the DLL in the JESD204B IP core.
The following figure shows the mapping scheme in the transport layer across various TX to RX interfaces for a specific system configuration.
Figure 4.  Mapping of Data Bit and Content Across Various Interfaces (LMF = 112, N = 12, N' = 16, S = 1, T represents the tail bits).