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1.1. JESD204B Design Example Quick Start Guide
1.2. Supported Configurations
1.3. Generic Design Example
1.4. Presets
1.5. Selecting and Generating the Design Example
1.6. Design Example with RTL State Machine Control Unit
1.7. JESD204B Intel® FPGA IP Design Example User Guide Document Archives
1.8. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
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1.6.2.1. Run-Time Reconfiguration
The JESD204B IP core supports run-time reconfiguration for the LMF and data rate settings. The design example only demonstrates the following set of configuration.
To generate the design example with run-time reconfiguration enabled, the LMF and bonding mode parameters must match the default value listed in the table below.
Parameter | Default | Run-time Reconfiguration |
---|---|---|
LMF | 222 | 112 |
FRAMECLK_DIV | 2 | 2 |
Data Rate | 6144 Mbps | 3072 Mbps |
Link Clock | 153.6 MHz | 76.8 MHz |
Frame Clock | 153.6 MHz | 76.8 MHz |
Bonding Mode | Non-bonded | Non-bonded |