JESD204B Intel® FPGA IP Design Example User Guide: Quartus® Prime Standard Edition

ID 683094
Date 7/19/2024
Public
Document Table of Contents

1.6.6. Generating the Design Example For Compilation

Use the gen_quartus_synth.tcl script to generate the JESD204B design example for compilation.
Note: If you use the Tcl console in the Quartus® Prime software to generate the gen_quartus_synth.tcl script, close all Quartus® Prime project before you start generating the script.

To run the Tcl script using the Quartus® Prime software, follow these steps:

  1. Launch the Quartus® Prime software.
  2. On the View menu, click Utility Windows and select Tcl Console.
  3. In the Tcl Console, type cd <example_design_directory>/ed_synth to go to the specified directory.
  4. Type source gen_quartus_synth.tcl to generate the JESD204B design example for compilation.

To run the Tcl script using the command line, follow these steps:

  1. Obtain the Quartus® Prime software resource.
  2. Type cd <example_design_directory>/ed_synth to go to the specified directory.
  3. Type quartus_sh -t gen_ed_quartus_synth.tcl to generate the JESD204B design example for compilation.