JESD204B Intel® FPGA IP Design Example User Guide: Quartus® Prime Standard Edition

ID 683094
Date 7/19/2024
Public
Document Table of Contents

1.1.1. Directory Structure

The JESD204B design example file directories contain generated files for the design examples.
Figure 2. Directory Structure for the JESD204B Design Example
Table 1.  Directory and File Description
Directory/File Description
ed_sim 1 The folder that contains the testbench files.

ed_sim/testbench/cadence

ed_sim/testbench/mentor

ed_sim/testbench/synopsys/vcs

The folder that contains the simulation script. It also serves as a working area for the simulator.
ed_synth 1 The folder that contains the design example synthesizable components.
ip_sim The folder that contains the simulation script to generate the JESD204B IP Core Verilog/VHDL simulation model.
1 Only for RTL State Machine Control design example.