JESD204B Intel® FPGA IP Design Example User Guide: Quartus® Prime Standard Edition

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ID 683094
Date 7/19/2024
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP Design Example User Guide
1. JESD204B Intel® FPGA IP Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. JESD204B Intel® FPGA IP Design Example User Guide Document Archives 1.8. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1. JESD204B Intel® FPGA IP Design Example User Guide

1.6.3. System Interface Signals

Table 33.  Interface Signals

Signal

Clock Domain

Direction

Description

Clocks and Resets
device_clk

—

Input

Device clock signal from the external converter or clock device.

mgmt_clk

—

Input

Management clock signal from the on-board 100 MHz oscillator.

frame_clk

—

Output

Internally generated clock. The Avalon-ST user data input must be synchronized to this clock domain for normal operation mode.

global_rst_n mgmt_clk

Input

Global reset signal from the push button. This reset is an active low signal and the deassertion of this signal is synchronous to the rising-edge of mgmt_clk.

Signal

Clock Domain

Direction

Description

JESD204B
tx_sysref[LINK-1:0] link_clk

Input

TX SYSREF signal for JESD204B Subclass 1 implementation.

sync_n[LINK-1:0] link_clk

Input

Indicates a TX SYNC_N from the receiver. This is an active low signal and is asserted 0 to indicate a synchronization request or error reporting.

mdev_sync_n[LINK-1:0] link_clk

Input

Indicates a multidevice synchronization request at the TX path. Synchronize signal combination should be done externally and then input to the JESD204B IP core through this signal. In a single link instance where multidevice synchronization is not needed, you need to tie this signal to the dev_sync_n signal.

alldev_lane_aligned link_clk

Input

Aligns all lanes for this device at the RX path.

For multidevice synchronization, multiplex all the dev_lane_aligned signals before connecting to this signal pin.

For single device support, connect the dev_lane_aligned signal back to this signal.

rx_sysref[LINK-1:0] link_clk

Input

RX SYSREF signal for JESD204B Subclass 1 implementation.

tx_dev_sync_n[LINK-1:0] link_clk

Output

Indicates a clean synchronization request at the TX path. This is an active low signal and is asserted 0 to indicate a synchronization request. The SYNC_N signal error reporting is masked out of this signal. This signal is also asserted during software-initiated synchronization.

dev_lane_aligned[LINK-1:0] link_clk

Output

Indicates that all lanes for this device are aligned at the RX path.

rx_dev_sync_n[LINK-1:0] link_clk

Output

Indicates a SYNC_N to the transmitter. This is an active low signal and is asserted 0 to indicate a synchronization request. Instead of reporting the link error through this signal, the JESD204B IP core uses the jesd204_rx_int signal to indicate an interrupt.

Signal

Clock Domain

Direction

Description

SPI
miso sclk

Input

Output data from a slave to the input of the master.

mosi sclk

Output

Output data from the master to the inputs of the slaves.

sclk mgmt_clk

Output

Clock driven by the master to slaves, to synchronize the data bits.

ss_n[2:0] sclk

Output

Active low select signal driven by the master to individual slaves, to select the target slave. Defaults to 3 bits.

Signal

Clock Domain

Direction

Description

Serial Data and Control
rx_serial_data[LINK*L-1:0]

—

Input

Differential high speed serial input data. The clock is recovered from the serial data stream.

tx_serial_data[LINK*L-1:0] device_clk

Output

Differential high speed serial output data. The clock is embedded in the serial data stream.

rx_seriallpbken[LINK*L-1:0]

—

Input

Assert this signal to enable internal serial loopback in the duplex transceiver.

Signal

Clock Domain

Direction

Description

User Request Control
reconfig mgmt_clk

Input

Active high reconfiguration request. Set this signal to static 0 during compile time if run time reconfiguration is not required.

runtime_lmf mgmt_clk

Input

Reconfigure the LMF value at run-time. This value must be stable prior to assertion of the reconfig signal.
  • 0—Downscale to the LMF value stored in MIF file.
  • 1— Upscale back to maximum LMF value.
Assuming at compile time, the LMF configuration is 222, set this signal to 0 to scale down the LMF configuration to 112. Set this signal to 1 to scale up the LMF configuration back to 222.
runtime_datarate mgmt_clk

Input

Reconfigure the data rate at run-time. This value must be stable prior to assertion of reconfig signal.

  • 0— Downscale to data rate setting stored in PLL, PHY, and clock MIF.
  • 1— Upscale back to maximum data rate setting stored in PLL, PHY, and clock MIF.

Assuming the compile time data rate is 3.072 Gbps, set this signal to 0 to scale down the data rate to 1.536 Gbps. Set this signal to 1 to scale up the data rate back to 3.072 Gbps.

cu_busy mgmt_clk

Output

Assert high to indicate that the control unit is busy. All reconfiguration input are ignored when this signal is high.

Signal

Clock Domain

Direction

Description

Avalon- ST User Data
avst_usr_din[(FRAMECLK_DIV*LINK*M*S*N)-1:0] frame_clk

Input

TX data from the Avalon-ST source interface. The source arranges the data in a specific order, as illustrated in the cases below:

Case 1: If F1/F2_FRAMECLK_DIV =1, LINK = 1, M = 1, S =1, N = 16:

  • avst_usr_din[15:0]

Case 2: If F1/F2_FRAMECLK_DIV =1, LINK = 1, M = 2 (denoted by m0 and m1), S =1, N = 16:

  • avst_usr_din[15:0] = m0[15:0]
  • avst_usr_din[31:16] = m1[15:0]

Case 3: If F1/F2_FRAMECLK_DIV =1, LINK = 2 (denoted by link0 and link1), M = 1, S =1, N = 16:

  • avst_usr_din[15:0] = link0
  • avst_usr_din[31:16] = link1

Case 4: If F1/F2_FRAMECLK_DIV =1, LINK = 2 (denoted by link0 and link1), M = 2 (denoted by m0 and m1), S =1, N = 16:

  • avst_usr_din[15:0] = link0, m0[15:0]
  • avst_usr_din[31:16] = link0, m1[15:0]
  • avst_usr_din[47:32] = link1, m0[15:0]
  • avst_usr_din[63:48] = link1, m1[15:0]
avst_usr_din_valid frame_clk

Input

Indicates whether the data from the Avalon-ST source interface to the transport layer is valid or invalid.

  • 0—data is invalid
  • 1—data is valid
avst_usr_din_ready frame_clk

Output

Indicates that the transport layer is ready to accept data from the Avalon-ST source interface.

  • 0—transport layer is not ready to receive data
  • 1—transport layer is ready to receive data
avst_usr_dout[(FRAMECLK_DIV*LINK*M*S*N)-1:0] frame_clk

Output

RX data to the Avalon-ST sink interface. The transport layer arranges the data in a specific order, as illustrated in the cases below:

Case 1: If F1/F2_FRAMECLK_DIV =1, LINK = 1, M = 1, S =1, N = 16:

  • avst_usr_dout[15:0]

Case 2: If F1/F2_FRAMECLK_DIV =1, LINK = 1, M = 2 (denoted by m0 and m1), S =1, N = 16:

  • avst_usr_dout[15:0] = m0[15:0]
  • avst_usr_dout[31:16] = m1[15:0]

Case 3: If F1/F2_FRAMECLK_DIV =1, LINK = 2 (denoted by link0 and link1), M = 1, S =1, N = 16:

  • avst_usr_dout[15:0] = link0
  • avst_usr_dout[31:16] = link1

Case 4: If F1/F2_FRAMECLK_DIV =1, LINK = 2 (denoted by link0 and link1), M = 2 (denoted by m0 and m1), S =1, N = 16:

  • avst_usr_dout[15:0] = link0, m0[15:0]
  • avst_usr_dout[31:16] = link0, m1[15:0]
  • avst_usr_dout[47:32] = link1, m0[15:0]
  • avst_usr_dout[63:48] = link1, m1[15:0]
avst_usr_dout_valid frame_clk

Output

Indicates whether the data from the transport layer to the Avalon-ST sink interface is valid or invalid.

  • 0—data is invalid
  • 1—data is valid
avst_usr_dout_ready

frame_clk

Input

Indicates that the Avalon-ST sink interface is ready to accept data from the transport layer.

  • 0—Avalon-ST sink interface is not ready to receive data
  • 1—Avalon-ST sink interface is ready to receive data
test_mode[3:0] frame_clk

Input

Specifies the operation mode.

  • 0000—Normal mode. The design example takes data from the Avalon-ST source.
  • 1000—Test mode. The design example generates alternate checkerboard data pattern.
  • 1001—Test mode. The design example generates ramp wave data pattern.
  • 1010—Test mode. The design example generates the PRBS data pattern.
  • Others—Reserved

Signal

Clock Domain

Direction

Description

Status
rx_is_lockedtodata [LINK*L-1:0] device_clk

Output

Asserted to indicate that the RX CDR PLL is locked to the RX data and the RX CDR has changed from LTR to LTD mode.

data_error [LINK-1:0] frame_clk

Output

Asserted to indicate that the pattern checker has found a mismatch in the received data and the expected data. One error signal per pattern checker.

jesd204_tx_int[LINK-1:0] link_clk

Output

Interrupt pin for the JESD204B IP core (TX). The interrupt signal is asserted when an error condition or synchronization request is detected.

jesd204_rx_int[LINK-1:0] link_clk

Output

Interrupt pin for the JESD204B IP core (RX). The interrupt signal is asserted when an error condition or synchronization request is detected.

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