JESD204B Intel® FPGA IP Design Example User Guide: Quartus® Prime Standard Edition

Download PDF
ID 683094
Date 7/19/2024
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP Design Example User Guide
1. JESD204B Intel® FPGA IP Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. JESD204B Intel® FPGA IP Design Example User Guide Document Archives 1.8. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1. JESD204B Intel® FPGA IP Design Example User Guide

1.6.1.7.1. Supported System Configuration

The transport layer supports static configurations where before compilation, you can modify the configurations using the IP core's parameter editor in the Quartus® Prime software. To change to another configuration, you have to recompile the design. The following list describes the supported configurations for the transport layer:

  • Data rate (maximum) = 12.5 Gbps (F1_FRAMECLK_DIV = 4 and F2_FRAMECLK_DIV = 2)
  • L = 1–8
  • F = 1, 2, 4, 8
  • N = 12, 13, 14, 15, 16
  • N' = 16
  • CS = 0–3
  • CF = 0
  • HD = 0 (for F=2, 4, 8), 1 (for F=1)

Dynamic Downscaling Of System Parameters (L, N, and F)

The Dynamic Downscaling of System Parameters (DDSP) feature enables you to dynamically downscale specific JESD204B system parameters through the CSR, without having to recompile the FPGA.

The transport layer supports dynamic downscaling of parameters L, F, and N only. The supported M and S parameters are determined by the L, F, and N' parameters. Some parameters (for example, CS and N') do not have this capability in the transport layer. If you needs to change any of these parameters, you must recompile the system.

You are advised to connect the power down channels to higher indexes and connect used channel at lower lanes. Otherwise, you have to reroute the physical-used channels to lower lanes externally when connecting the IP core to the transport layer. For example, when L = 4 and csr_l = 8'd1 (which means two lanes out of four lanes are active), with lane 1 and lane 3 being powered down, connection from the MAC to the transport layer for lane 0 remains. However, lane 1 is powered down while lane 2 is not powered down. Thus, lane 2 output from the MAC should be rerouted to lane 1 data input of the transport layer. The data port for those power-down channels will be tied off within the transport layer.

The 16-bit N' data for F = 1 is formed through the data from 2 lanes. Thus, F = 1 is not supported for odd number of lanes, for example, when LMF = 128. In this case, you can only reconfigure from F = 8 to F = 4 and F = 2 but not F = 1.

Relationship Between Frame Clock and Link Clock

The frame clock and link clock are synchronous.

The ratio of link_clk period to frame_clk period is given by this formula: 

32 x L / (M x S x N')

Table 15.   txframe_clk and rxframe_clk Frequency for Different F Parameter Settings For a given f txlink (txlink_clk frequency) and f rxlink (rxlink_clk frequency), the f txframe (txframe_clk frequency) and f rxframe (rxframe_clk frequency) are derived from the formula listed in this table.
F Parameter f txframe (txframe_clk frequency) f rxframe (rxframe_clk frequency)
1 ftxlink x (4 / F1_FRAMECLK_DIV ) frxlink x (4 / F1_FRAMECLK_DIV )
2 ftxlink x (2 / F2_FRAMECLK_DIV ) frxlink x (2 / F2_FRAMECLK_DIV )
4 ftxlink frxlink
8 ftxlink / 2 frxlink / 2
Level Two Title