JESD204B Intel® FPGA IP Design Example User Guide: Quartus® Prime Standard Edition

ID 683094
Date 7/19/2024
Public
Document Table of Contents

1.6.1.6. Pattern Checker

The pattern checker instantiates any supported checkers and support run time reconfiguration (downscale) of the number of converters per device (M) and samples per converter per frame (S).

The pattern checker can be either a parallel PRBS checker, alternate checkerboard checker, or ramp wave checker. The data input bus width of the pattern checker is equivalent to the value of FRAMECLK_DIV × M × S × N.

The pattern checker includes an ERR_THRESHOLD parameter to control the number of error tolerance allowed in the checker. The default value of this parameter is 1.

The pattern checker also includes a REVERSE_DATA parameter to control data arrangement at the input. The default value of this parameter is 0.

  • 0—no data rearrangement at the input of the checker.
  • 1—data rearrangement at the input of the checker.