JESD204B Intel® FPGA IP Design Example User Guide: Quartus® Prime Standard Edition
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Visible to Intel only — GUID: bhc1411116842348
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1.6.5.1. Generating the Design Example Simulation Model
After generating the IP core, generate the design example simulation testbench using the script (gen_ed_sim_verilog.tcl or gen_ed_sim_vhdl) located in the <example_design_directory>/ed_sim directory.
To run the Tcl script using the Quartus® Prime software, follow these steps:
- Launch the Quartus® Prime software.
- On the View menu, click Utility Windows and select Tcl Console.
- In the Tcl Console, type cd <example_design_directory>/ed_sim to go to the specified directory.
- Type source gen_ed_sim_verilog.tcl (Verilog) or source gen_ed_sim_vhdl.tcl (VHDL) to generate the simulation files.
To run the Tcl script using the command line, follow these steps:
- Obtain the Quartus® Prime software resource.
- Type cd <example_design_directory>/ed_sim to go to the specified directory.
- Type quartus_sh -t gen_ed_sim_verilog.tcl (Verilog) or quartus_sh -t gen_ed_sim_vhdl.tcl (VHDL) to generate the simulation files.