JESD204B Intel® FPGA IP Design Example User Guide: Quartus® Prime Standard Edition

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Date 7/19/2024
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP Design Example User Guide
1. JESD204B Intel® FPGA IP Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. JESD204B Intel® FPGA IP Design Example User Guide Document Archives 1.8. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1. JESD204B Intel® FPGA IP Design Example User Guide

1.6.1.7.3. TX Path

The assembler in the TX path consists of the tail bits padding, assembling, and multiplexing blocks.
Figure 5. TX Path Assembler Block Diagram


  • Tail bits padding block—pads incoming data (jesd204_tx_datain) with "0" if N < 16, so that the padded data is 16 bits per sample.
  • Assembling block—arranges the resulting data bits in a specific way according to the mapping scheme (refer to figure).
  • Multiplexing block—sends the multiplexed data to the DLL interface, determined by certain control signals from the TX control block.
Table 16.  Assembler Parameter Settings
Parameter Description Value
L Number of lanes per converter device. 1–8
F Number of octets per frame. 1, 2, 4, 8
CS Number of control bits per conversion sample. 0–3
N Number of conversion bits per converter. 12-16
N' Number of transmitted bits per sample in the user data format. 16
F1_FRAMECLK_DIV Only applies to cases where F=1.

The divider ratio on the frame_clk. The assembler always use the post-divided frame_clk (txframe_clk). 6

1, 4
F2_FRAMECLK_DIV Only applies to cases where F=2.

The divider ratio on the frame_clk. The assembler always use the post-divided frame_clk (txframe_clk). 6

1, 2
RECONFIG_EN Enable reconfiguration support in the transport layer. Only downscaling reconfiguration is supported. Disable the reconfiguration to reduce the logic. 0, 1
DATA_BUS_WIDTH The data input bus width size that depends on the F and L.

bus_width = M*S*N

F = (M*S*N_PRIME)/(8*L)

M*S = (8*F*L)/N_PRIME

Therefore the data bus width = (8*F*L*N)/N_PRIME

(8*F*L*N)/N_PRIME
CONTROL_BUS_WIDTH The control input bus width size. The width depends on the CS parameter as well as the M and S parameters. When CS is 0, the control data is one bit wide (tie the signal to 0).

If CS = 0, the bus width = 1. Otherwise, the bus width = (DATA_BUS_WIDTH/N*CS) while DATA_BUS_WIDTH/N = M*S

OUTPUT_BUS_WIDTH/N*CS
Table 17.  Assembler Signals

Signal

Clock Domain

Direction

Description

Control Unit
txlink_clk

—

Input

TX link clock signal. This clock is equal to the TX data rate divided by 40. This clock is synchronous to the txframe_clk signal.
txframe_clk

—

Input

TX frame clock used by the transport layer. The frequency is a function of parameters F, F1_FRAMECLK_DIV, F2_FRAMECLK_DIV and txlink_clk.

This clock is synchronous to the txlink_clk signal.

txlink_rst_n txlink_clk

Input

Reset for the TX link clock domain logic in the assembler. This reset is an active low signal and the deassertion is synchronous to the rising-edge of txlink_clk.
txframe_rst_n txframe_clk

Input

Reset for the TX frame clock domain logic in the assembler. This reset is an active low signal and the deassertion is synchronous to the rising-edge of txframe_clk.

Signal

Clock Domain

Direction

Description

Between Avalon- ST and Transport Layer
jesd204_tx_ datain[(DATA_BUS_WIDTH)-1:0] txframe_clk

Input

TX data from the Avalon-ST source interface. The source shall arrange the data in a specific order, as illustrated in the cases listed in TX Path Data Remapping section
jesd204_tx_controlin[(CONTROL_BUS_WIDTH)-1:0] txframe_clk Input TX control data from the Avalon-ST source interface. The source shall arrange the data in a specific order, as illustrated in the cases listed in TX Path Data Remapping section
jesd204_tx_data_valid txframe_clk

Input

Indicates whether the data from the Avalon-ST source interface to the transport layer is valid or invalid.
  • 0—data is invalid
  • 1—data is valid
jesd204_tx_data_ready

txframe_clk

Output

Indicates that the transport layer is ready to accept data from the Avalon-ST source interface.

  • 0—transport layer is not ready to receive data
  • 1—transport layer is ready to receive data

Signal

Clock Domain

Direction

Description

Between Transport Layer and DLL
jesd204_tx_link_datain[(L*32)-1:0]

txlink_clk

Output

Indicates transmitted data from the transport layer to the DLL at txlink_clk clock rate, where four octets are packed into a 32-bit data width per lane. The data format is big endian. The table below illustrates the data mapping for L = 4:
jesd204_tx_link_datain [x:y] Lane
[31:0] 0
[63:32] 1
[95:64] 2
[127:96] 3

Connect this signal to the TX DLL jesd204_tx_link_data[] input pin.

jesd204_tx_link_data_valid

txlink_clk

Output

Indicates whether the jesd204_tx_link_datain[] is valid or invalid.
  • 0—jesd204_tx_link_datain[] is invalid
  • 1—jesd204_tx_link_datain[] is valid

Connect this signal to the TX DLL jesd204_tx_link_valid input pin.

jesd204_tx_link_early_ready 7 txlink_clk

Input

Indicates that the DLL requires valid data at the subsequent implementation-specific duration.

Connect this signal to the TX DLL jesd204_tx_frame_ready output pin.

jesd204_tx_link_error

txlink_clk

Output

Indicates an error at the Avalon-ST source interface. Specifically, this signal is asserted when jesd204_tx_data_valid = "0" while jesd204_tx_data_ready = "1". The DLL subsequently reports this error to the CSR block.

Connect this signal to the TX DLL jesd204_tx_frame_error input pin.

Signal

Clock Domain

Direction

Description

CSR in DLL
csr_l[4:0] 8 mgmt_clk

Input

Indicates the number of active lanes for the link. This 5-bit bus represents the L value in zero-based binary format. For example, if L = 1, the csr_l[4:0] = "00000". This design example supports the following values:
  • 00000
  • 00001
  • 00011
  • 00111
Any programmed value beyond the supported range may result in undeterminable behavior in the transport layer. You must ensure that the csr_l[4:0] value always matches the system parameter L value when it is in static configuration.

Runtime reconfiguration supports L fallback. For static configuration, set the maximum L and reconfigure csr_l[] to a smaller value during runtime. This transport layer only supports higher index channels to be powered down. To interleave the de-commision channels, you need to modify the interface connection from the DLL to transport layer.

Connect this signal to the TX DLL csr_l[] output pin.

csr_f[7:0] 8 mgmt_clk

Input

Indicates the number of octets per frame. This 8-bit bus represents the F value in zero-based binary format. For example, if F = 2, the csr_f[7:0] = "00000001". This design example supports the following values:
  • 00000000
  • 00000001
  • 00000011
  • 00000111

Any programmed value beyond the supported range may result in undeterminable behavior in the transport layer. Ensure that the csr_f[7:0] value always matches the system parameter F value when it is in static configuration. Connect this signal to the TX DLL csr_f[] output pin.

csr_n[4:0] 8 mgmt_clk

Input

Indicates the converter resolution. This 5-bit bus represents the N value in zero-based binary format. For example, if N = 16, the csr_n[4:0] = "01111". This design example supports the following values:
  • 01011
  • 01100
  • 01101
  • 01110
  • 01111
Any programmed value beyond the supported range may result in undeterminable behavior in the transport layer. You must ensure that the csr_n[4:0] value always match the system parameter N value.

Connect this signal to the TX DLL csr_n[] output pin.

TX Path Operation

The data transfer protocol between the Avalon-ST interface and the TX path transport layer is data transfer with backpressure, where ready_latency = 0.

Figure 6. TX Operation BehaviorThis figure shows the data transmission for a system configuration of LMF = 112, N = N' = 16, S = 1.

Operation:

  • Upon the deassertion of the txframe_rst_n signal, the jesd204_tx_link_early_ready signal from the DLL to the transport layer is asserted some time later, which activates the transport layer to start sampling the jesd204_tx_datain[15:0] signal from the Avalon-ST interface.
  • Each sampled 16-bit data is first written in a FIFO with a depth of four.
  • Once the FIFO accumulates 32-bit data, the data is streamed to the DLL accordingly through the jesd204_tx_link_datain[31:0] signal.
  • Finally, the jesd204_tx_link_early_ready and jesd204_tx_data_ready signals deassert because the DLL has entered code group synchronization state in this scenario.


TX Data Transmission

This section explains the data transmission behavior when there is a valid TX data out from the TL to DLL.

Upon the deassertion of txframe_rst_n signal, the link's jesd204_tx_link_early_ready signal equals to "1". This setting activates the TL to start sampling jesd204_tx_datain signal from the Avalon-ST interface and transmits sampled data (jesd204_tx_link_datain) to the TX link. The TX link only captures valid data from the TL when the jesd204_tx_link_ready signal equals to "1" (in user data phase). This means all the data transmitted from the TL before jesd204_tx_link_ready signal equals to "1" are ignored.

Figure 7. TX Data Transmission


Figure 8. TX Data Transmission (For F = 8)


TX Path Data Remapping

The JESD204B IP core implements the data transfer in big endian format.
Figure below illustrates the converter sample to transceiver lane mapping operation in the transport layer. Each converter sample has N bits, M converters per ADC/DAC device, and S samples per converter (M) per frame clock cycle. The transport layer operates at full rate or FRAMECLK_DIV=1.
  1. The application layer or user logic data path interfaces directly with the transport layer through the Avalon-ST data bus if the application layer operates in frame clock domain. If the application layer operates at a different clock domain than the frame clock domain, add a FIFO for the clock domain crossing.
  2. You have to reorder the samples so that sample 0 of converter 0 is located at LSB of the Avalon-ST data bus, followed by sample 1 of converter 0 (if S>1) or sample 0 of converter 1 (if S=1). The most significant bits (MSB) of the Avalon-ST bus has a sample of S -1 of converter M-1. For example, if S=4 and M=4, the most significant bits will be occupied by sample 3 of converter 3.
  3. In this example, there is no control word because CF=0. Control bits are added if CS>1. Depending on the value of CS and N, the number of tail bits added is N'-N-CS. For example, N'=16, N=12 and CS=2, the number of tail bits added to form a nibble group (NG) is 2.
  4. The JESD204B IP core implements the data transfer in big endian format. Data is reshuffled in big endian format before crossing to the link clock domain through an adaptor.
  5. The data is arranged so that the L0 is always on the right (LSB) in the data bus interfacing with the JESD204B IP core. In big endian implementation, the oldest data (F0) is placed at the MSB in L0. 32-bits or 4 octets of data are transferred to the IP core in one link clock cycle. For example of F=8, 2 link clock cycles are needed to transfer all 8 octets to the IP core.
Figure 9. User Data Format that Feeds into the Transport Layer and Output to the Link Layer

The following tables show examples of data mapping for L=4, F=1, 2, 4, 8 and M*S=2, 4, 8, 16. The configurations that the transport layer support are not limited to these examples.

Table 18.  Data Mapping for F=1, L=4
F = 1
Supported M and S M*S=2 for F=1, L=4

F=1 supports either (case1: M=1, S=2) or (case2: M=2, S=1)

F1_FRAMCLK_DIV=19 1st frameclk jesd204_tx_datain[31:0] = {F8F12, F0F4} Case1: M=1, S=2 M0S0=F0F4, M0S1=F8F12
Case2: M=2, S=1 M0S0=F0F4, M1S0=F8F12
2nd frameclk jesd204_tx_datain[31:0] = {F9F13, F1F5} Case1: M=1, S=2 M0S0=F1F5, M0S1=F9F13
Case2: M=2, S=1 M0S0=F1F5, M1S0=F9F13
3rd frameclk jesd204_tx_datain[31:0] = {F10F114, F2F6} Case1: M=1, S=2 M0S0=F2F6, M0S1=F10F14
Case2: M=2, S=1 M0S0=F2F6, M1S0=F10F14
4th frameclk jesd204_tx_datain[31:0] = {F11F15, F3F7} Case1: M=1, S=2 M0S0=F3F7, M0S1=F11F15
Case2: M=2, S=1 M0S0=F3F7, M1S0=F11F15
F1_FRAMCLK_DIV=4 10 jesd204_tx_datain[127:0] = {{F11F15, F3F7},{F10F114, F2F6},{F9F13, F1F5},{F8F12, F0F4}}
Lane L3 L2 L1 L0
Data Out {F12, F13, F14, F15} {F8, F9, F10, F11} {F4, F5, F6, F7} {F0, F1, F2, F3}
Table 19.  Data Mapping for F=2, L=4
F = 2
Supported M and S M*S=4 for F=2, L=4

F=2 supports either (case1: M=1, S=4), (case2: M=2, S=2) or (case3: M=4, S=1)

F2_FRAMCLK_DIV=1 1st frameclk

jesd204_tx_datain[63:0] = {F12F13, F8F9,F4F5, F0F1}

Case1: M=1, S=4 M0S0=F0F1, M0S1=F4F5, M0S2=F8F9, M0S3=F12F13 at
Case2: M=2, S=2 M0S0=F0F1, M0S1=F4F5, M1S0=F8F9, M1S1=F12F13
Case3: M=4, S=1 M0S0=F0F1, M1S0=F4F5, M2S0=F8F9, M3S0=F12F13
2nd frameclk

jesd204_tx_datain[63:0] = {F14F15, F10F11,F6F7, F2F3}

Case1: M=1, S=4 M0S0=F2F3, M0S1=F6F7, M0S2=F10F11, M0S3=F14F15
Case2: M=2, S=2 M0S0=F2F3, M0S1=F6F7, M1S0=F10F11, M1S1=F14F15
Case3: M=4, S=1 M0S0=F2F3, M1S0=F6F7, M2S0=F10F11, M3S0=F14F15
F2_FRAMCLK_DIV=2

jesd204_tx_datain[127:0] = {{F14F15, F10F11,F6F7, F2F3}, {F12F13, F8F9,F4F5, F0F1}}

Lane L3 L2 L1 L0
Data Out {F12, F13, F14, F15} {F8, F9, F10, F11} {F4, F5, F6, F7} {F0, F1, F2, F3}
Table 20.  Data Mapping for F=4, L=4
F = 4
Supported M and S M*S=8 for F=4, L=4

F=4 supports either (case1: M=1, S=8), (case2: M=2, S=4), (case3: M=4, S=2) or (case4: M=8, S=1)

F=4

jesd204_tx_datain[127:0] = {F14F15,F12F13, F10F11, F8F9,F6F7,F4F5, F2F3,F0F1}

Case1: M=1, S=8 {M0S7, M0S6, M0S5, M0S4, M0S3, M0S2, M0S1, M0S0}
Case2: M=2, S=4 {M1S3, M1S2, M1S1, M1S0, M0S3, M0S2, M0S1, M0S0}
Case3: M=4, S=2 {M3S1, M3S0, M2S1, M2S0, M1S1, M1S0, M0S1, M0S0}
Case4: M=8, S=1 {M7S0, M6S0, M5S0, M4S0, M3S0, M2S0, M1S0, M0S0}
Lane L3 L2 L1 L0
Data Out {F12, F13, F14, F15} {F8, F9, F10, F11} {F4, F5, F6, F7} {F0, F1, F2, F3}
Table 21.  Data Mapping for F=8, L=4
F = 8
Supported M and S M*S=16 for F=8, L=4

F=8 supports either (case1: M=1, S=16), (case2: M=2, S=8), (case3: M=4, S=4), (case4: M=8, S=2) or (case5: M=16, S=1)

F=8

jesd204_tx_datain[255:0] = {{F3031, F28F29,F26F27, F24F25}, {F22F23, F20F21,F18F19, F16F17}, {F14F15, F12F13,F10F11, F8F9}, {F6F7,F4F5, F2F3,F0F1}}

Case1: M=1, S=16 {M0S15, M0S14, M0S13, M0S12, M0S11, M0S10, M0S9, M0S8, M0S7, M0S6, M0S5, M0S4, M0S3, M0S2, M0S1, M0S0}
Lane L3 L2 L1 L0
Data Out at linkclk T0 {F24, F25, F26, F27} {F16, F17, F18, F19} {F8, F9, F10, F11} {F0, F1, F2, F3}
Data Out at linkclk T1 {F28, F29, F30, F31} {F20, F21, F22, F23} {F12, F13, F14, F15} {F4, F5, F6, F7}

TX Error Reporting

For TX path error reporting, the transport layer expects a valid stream of TX data from the Avalon-ST interface (indicated by jesd204_tx_data_valid signal = 1) as long as the jesd204_tx_data_ready remains asserted. If the jesd204_tx_data_valid signal unexpectedly deasserts during this stage, the transport layer reports an error to the DLL by asserting the jesd204_tx_link_error signal and deasserting the jesd204_tx_link_data_valid signal accordingly, as shown in the timing diagram below.

Figure 10. TX Error ReportingThe jesd204_tx_data_valid signal deasserts for one frame_clk and cannot be sampled by the link_clk.


TX Latency

Table 22.   TX Latency Associated with Different F and FRAMECLK_DIV Settings.
F FRAMECLK_DIV TX Latency
1 1 3 txframe_clk period.
  • Maximum 5 txframe_clk period for byte 3
  • Minimum 2 txframe_clk period for byte 0
1 4 1 txframe_clk period
2 1 3 txframe_clk period.
  • Maximum 4 txframe_clk period for byte 2 and byte 3
  • Minimum 3 txframe_clk period for byte 0 and byte 1
2 2 1 txframe_clk period
4 — 1 txframe_clk period
8 — 1 txframe_clk period
6 Refer to the txframe_clk and rxframe_clk frequencies table to set the desired frame clock frequency with different FRAMECLK_DIV and F values.
7 If a JESD device of No Multiple-Converter Device Alignment, Single-Lane (NMCDA-SL) class is deployed, Intel® recommends that you tie this input signal to "1".
8 This signal should be static and valid before the deassertion of the link_rst_n and frame_rst_n signals.
9 The effective frame clock in the Transport Layer is 4x of the link clock.
10 The effective frame clock in the Transport Layer is same as the link clock.
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