JESD204B Intel® FPGA IP Design Example User Guide: Quartus® Prime Standard Edition

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ID 683094
Date 7/19/2024
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP Design Example User Guide
1. JESD204B Intel® FPGA IP Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. JESD204B Intel® FPGA IP Design Example User Guide Document Archives 1.8. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1. JESD204B Intel® FPGA IP Design Example User Guide

1.6.1.3. Transceiver Reconfiguration Controller

The transceiver reconfiguration controller allows you to change the device transceiver settings at any time. Any portion of the transceiver can be selectively reconfigured. Each portion of the reconfiguration requires a read-modify-write operation (read first, then write), in such a way that it modifies only the appropriate bits in a register and not changing other bits.

In the design example, MIF approach is used to reconfigure the ATX PLL and transceiver channel in the JESD204 IP core via the Transceiver Reconfiguration Controller. The number of reconfiguration interface is determined by number of lanes (L) + number of TX_PLL (different number of TX_PLL for bonded and non-bonded mode). Since the MIF approach reconfiguration for transceiver only supports non-bonded mode, the number of TX_PLL is equal to number of lanes. The number of reconfiguration interface = 2 x number of lanes (L).

The transceiver reconfiguration controller interfaces:

  • MIF Reconfiguration Avalon-MM master interface—connects to the MIF ROM.
  • Transceiver Reconfiguration interface—connects to the JESD204B IP core, which eventually connects to the native PHY.
  • Reconfiguration Management Avalon-MM slave interface—connects to the control unit.
Note: The transceiver reconfiguration controller is only used in Arria V and Stratix V devices. For Arria 10 devices, the control unit directly communicates with the transceiver in the JESD204B IP core through the reconfig_avmm_* interface signals.

The following transceiver reconfiguration controller Avalon-MM operations are involved during data rate reconfiguration.

Table 10.   Transceiver Reconfiguration Controller Operation for Arria V and Stratix V Devices
Operation Avalon-MM Interface Signal Byte Address Offset (6bits) Bit Value
Write logical channel number reconfig_mgmt_* 0x38 [9:0] 0
Write MIF mode reconfig_mgmt_* 0x3A [3:2] 2'b00
Write 0 to streamer offset register reconfig_mgmt_* 0x3B [15:0] 0
Write MIF base address to streamer data register reconfig_mgmt_* 0X3C [31:0] *32'h1000
Initiate a write of all the above data reconfig_mgmt_* 0x3A [0] 1'b1
Write 1 to streamer offset register reconfig_mgmt_* 0x3B [15:0] 1
Write to streamer data register to set up MIF streaming reconfig_mgmt_* 0x3C [31:0] 3
Initiate a write of all the above data to start streaming the MIF reconfig_mgmt_* 0x3A [0] 1'b1
Read the busy bit to determine when the write has completed reconfig_mgmt_* 0x3A [8]

1: Busy

0: Operation completed

Note: The above steps are repeated for the number of channels and followed by the number of TX_PLLs.

For Arria 10 devices, the only Avalon-MM operation is a direct write to the transceiver register through the reconfig_avmm_* interface at the JESD204B IP core. Every line in the MIF is DPRIO_ADDR[25:16]+ BIT_MASK[15:8]+ DATA[7:0]. The control unit maps the DPRIO_ADDR to reconfig_avmm_address and BIT_MASK + DATA to reconfig_avmm_data.

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