JESD204B Intel® FPGA IP Design Example User Guide: Quartus® Prime Standard Edition

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ID 683094
Date 7/19/2024
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP Design Example User Guide
1. JESD204B Intel® FPGA IP Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. JESD204B Intel® FPGA IP Design Example User Guide Document Archives 1.8. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1. JESD204B Intel® FPGA IP Design Example User Guide

1.5. Selecting and Generating the Design Example

You can access and generate the IP core design example through the IP Catalog parameter editor.

Follow the steps below to launch the design example GUI and generate the design example.

  1. In the IP Catalog (Tools > IP Catalog), select the JESD204B IP core.
  2. Specify an entity name and location for your custom IP variation. This name identifies the IP core variation files in your project. If prompted, also specify the target Intel® FPGA device family. Click OK.
  3. In the parameter editor, click on the IP tab and set the JESD204B IP core parameters as per your specifications. If you want to pre-fill the parameters with the set of parameter values that result in a valid example design, use the presets in the Presets tab. Refer to Presets for more details.
  4. In the parameter editor, click on the Example Design tab.
  5. Under the Available Example Designs section, select the available designs. The options you can select are based on the design examples that are available.
    • None: No design example available that matches the IP parameters selected.
    • RTL State Machine Control: Design example has RTL state machine as control unit.
  6. If the Select Design option under the Available Example Designs section displays None, the Generate generic example design selection appears. In the Generate generic example design list, select one of the options available to generate a generic design example.
    • No: No generic design example is generated.
    • Generic RTL State Machine Control: Generic design example has RTL state machine as control unit.
    Note: The generic design example parameter selection may not match the parameters that you selected in the IP tab. You can modify the generated generic design example files to match your desired IP parameter settings.
  7. Under the Example Design Files section, select the desired design example files. The options you can select are based on the design examples that are available.
    • Simulation: Generate simulation files.
    • Synthesis: Generate synthesis files.
  8. Under the Generated HDL Format for Simulation section (only available if the Simulation option is checked), select the desired HDL format. The options you can select are based on the design examples that are available.
  9. Under the Generated HDL Format for Synthesis section (only available if the Synthesis option is checked), select the desired HDL format. The options you can select are based on the design examples that are available.
  10. Under the Target Development Kit section, select the development kit for the design example to target. The options you can select are based on the design example that are available.
    • None: Design example does not target any board. The target device is set to a default device and may not match your selected target device in the Quartus project.
    • Arria 10 GX FPGA Development Kit: Design example is targeted for Arria 10 GX FPGA development kit. This option is available for Arria 10 devices only. The target device is Arria 10 GX FPGA and may not match your selected target device in the Quartus project.
    Note: The hardware example design targets an Arria 10 ES3 device. It cannot function correctly on an Arria 10 production device.
  11. Click the Generate Example Design button on the top right corner to generate the design example based on your settings.
    1. If the selected design example in step 5 is None, and the generate generic design example selection in step 6 is No, an error message is displayed and no design example is generated.
    2. If the selected design example in step 5 is RTL State Machine Control, the relevant design example is generated with the JESD204B parameters matching the JESD204B IP parameter settings in the IP tab.
    3. If the selected design example in step 5 is None, and the generate generic design example selection from Step 6 is Generic RTL State Machine Control, the relevant generic design example is generated with the pre-set JESD204B parameters. You can then modify the JESD204B parameters directly in the generated design files to match your desired parameter settings.

The design example files are generated in the folder that you specified when you clicked on Generate Example Design. This is a self-contained design example folder that is in the same directory that contains the generated IP files. All the files necessary to compile and run the design example, including an independently generated JESD204B IP core module that is separate from the core module generated from the IP tab is stored in this folder and its sub directories.

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