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1.1. JESD204B Design Example Quick Start Guide
1.2. Supported Configurations
1.3. Generic Design Example
1.4. Presets
1.5. Selecting and Generating the Design Example
1.6. Design Example with RTL State Machine Control Unit
1.7. JESD204B Intel® FPGA IP Design Example User Guide Document Archives
1.8. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
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1.3. Generic Design Example
If the JESD204B IP parameters that you select does not match any design example that is available, there is an option for you to generate a generic design example.
A generic design example is a design that has pre-selected IP parameters that matches the list of supported IP parameters for the design example.
Note: The generated generic example design may have IP parameters that differ from the parameters of your IP core. Modify the generic example design according to your system specifications.
The table below lists the parameters in the generic design example.
JESD204B IP Parameters | Design Example |
---|---|
Generic RTL State Machine Control | |
Devices Support | V series and Arria 10 |
L | 2 |
M | 2 |
F | 2 |
K | 16 |
S | 1 |
Wrapper Options | Both Base and Phy |
Data Path | Duplex |
JESD204B Subclass | 1 |
Data Rate | 6144 |
PCS Option | Enabled Hard PCS |
PLL Type | CMU 4 |
Bonding Mode | Bonded |
Enable Transceiver Dynamic Reconfiguration | No |
PLL/CDR Reference Clock Frequency | 153.6 |
Enable Bit Reversal And Byte Reversal | No |
N | 16 |
N’ | 16 |
CS | 0 |
CF | 0 |
High Density User Data Format (HD) | 0 |
Enable scramble (SCR) | Yes |
Enable Error Code Correction (ECC_EN) | Yes |
4 Not applicable to Arria 10 devices.