Stratix® 10 Device Family Pin Connection Guidelines

Download PDF
ID 683028
Date 12/19/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 Device Family Pin Connection Guidelines
1. Stratix® 10 Device Family Pin Connection Guidelines x
1.1. Stratix® 10 Core Pins 1.2. Stratix® 10 High Bandwidth Memory (HBM) Pins 1.3. H-Tile and L-Tile Pins 1.4. Stratix® 10 E-Tile Pins 1.5. Stratix® 10 P-Tile Pins 1.6. Stratix® 10 Hard Processor System (HPS) Pins 1.7. Power Supply Sharing Guidelines for Stratix® 10 Devices 1.8. Document Revision History for the Stratix® 10 Device Family Pin Connection Guidelines
1.1. Stratix® 10 Core Pins x
1.1.1. Clock and PLL Pins 1.1.2. Dedicated Configuration/JTAG Pins 1.1.3. Optional/Dual-Purpose Configuration Pins 1.1.4. 3 V Compatible I/O Pins 1.1.5. 3.3 V I/O Pins 1.1.6. Differential I/O Pins 1.1.7. External Memory Interface Pins 1.1.8. Voltage Sensor Pins 1.1.9. Temperature Sensor Pins 1.1.10. Reference Pins 1.1.11. No Connect and DNU Pins 1.1.12. Power Supply Pins 1.1.13. Secure Device Manager (SDM) Pins 1.1.14. Secure Device Manager (SDM) Optional Signal Pins 1.1.15. Notes to Stratix® 10 Core Pins
1.2. Stratix® 10 High Bandwidth Memory (HBM) Pins x
1.2.1. UIB and eSRAM Pins 1.2.2. Stratix® 10 HBM Power Supply Pins 1.2.3. Notes to Stratix® 10 HBM Pins
1.3. H-Tile and L-Tile Pins x
1.3.1. H-Tile and L-Tile Pins
1.4. Stratix® 10 E-Tile Pins x
1.4.1. Stratix® 10 E-Tile Pins 1.4.2. Notes to Stratix® 10 E-Tile Pins
1.5. Stratix® 10 P-Tile Pins x
1.5.1. Stratix® 10 P-Tile Power Supply Pins 1.5.2. Stratix® 10 P-Tile Transceiver Pins
1.6. Stratix® 10 Hard Processor System (HPS) Pins x
1.6.1. HPS Supply Pins 1.6.2. HPS Oscillator Clock Input Pin 1.6.3. HPS JTAG Pins 1.6.4. HPS GPIO Pins 1.6.5. HPS SDMMC Pins 1.6.6. HPS NAND Pins 1.6.7. HPS USB Pins 1.6.8. HPS EMAC Pins 1.6.9. HPS I2C_EMAC and MDIO Pins 1.6.10. HPS I2C Pins 1.6.11. HPS SPI Pins 1.6.12. HPS UART Pins 1.6.13. HPS Trace Pins 1.6.14. Notes to Stratix® 10 HPS Pins
1.7. Power Supply Sharing Guidelines for Stratix® 10 Devices x
1.7.1. Example 1— Stratix® 10 GX 1.7.2. Example 2— Stratix® 10 GX 1.7.3. Example 3— Stratix® 10 GX (only for the HF35 Package) 1.7.4. Example 4— Stratix® 10 GX (only for the HF35 Package) 1.7.5. Example 5— Stratix® 10 SX (–1V, –2V, and –3V parts) 1.7.6. Example 6— Stratix® 10 SX (–2L and –3X parts) 1.7.7. Example 7— Stratix® 10 SX (–1V, –2V, and –3V parts) 1.7.8. Example 8— Stratix® 10 SX (–2L and –3X parts) 1.7.9. Example 9— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) 1.7.10. Example 10— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) 1.7.11. Example 11— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) 1.7.12. Example 12— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) 1.7.13. Example 13— Stratix® 10 MX (–1V, –2V, and –3V parts) 1.7.14. Example 14— Stratix® 10 MX (–1V, –2V, and –3V parts) 1.7.15. Example 15— Stratix® 10 MX (E-Tile) 1.7.16. Example 16— Stratix® 10 TX (–1V, –2V, and –3V parts) 1.7.17. Example 17— Stratix® 10 TX (–2L and –3X parts) 1.7.18. Example 18— Stratix® 10 DX (–1V, –2V, and –3V parts) 1.7.19. Example 19— Stratix® 10 GX 10M 1.7.20. Example 20— Stratix® 10 GX 10M
1. Stratix® 10 Device Family Pin Connection Guidelines

1.1.13. Secure Device Manager (SDM) Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Note: The Stratix® 10 GX 10M device has two independent SDM, one for each die.
Table 13.  SDM Pins (See Note 11)
Pin Name ( Stratix® 10 Devices) Pin Name ( Stratix® 10 GX 10M Device) Pin Description MSEL[2:0] Pin Functions Connection Guidelines
RREF_SDM

F1_RREF_SDM

F2_RREF_SDM

Reference resistor input for the PLLs of the SDM interface.

— Input

Connect a 2 kΩ ±1% resistor to GND.

SDM_IO0 F[1,2]_SDM_IO0

This pin is pulled low internally by a 25-kΩ resistor when the device is powered up.

Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO1 F[1,2]_SDM_IO1

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

3'b110 AVSTx8_DATA2 Connect this pin to the data2 pin of an external configuration controller when configuring using the Avalon® streaming x8 interface.
3'b001 or 3'b011 AS_DATA1 Connect this pin to the data1 pin of the QSPI flash device when configuring from the QSPI flash device.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO2 F[1,2]_SDM_IO2

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

3'b110 AVSTx8_DATA0 Connect this pin to the data0 pin of an external configuration controller when configuring using the Avalon® streaming x8 interface.
3'b001 or 3'b011 AS_CLK Connect this pin to the clock input of the QSPI flash device when configuring from the QSPI flash device.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO3 F[1,2]_SDM_IO3

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

3'b110 AVSTx8_DATA3 Connect this pin to the data3 pin of an external configuration controller when configuring using the Avalon® streaming x8 interface.
3'b001 or 3'b011 AS_DATA2 Connect this pin to the data2 pin of the QSPI flash device when configuring from the QSPI flash device.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO4 F[1,2]_SDM_IO4

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

3'b110 AVSTx8_DATA1 Connect this pin to the data1 pin of an external configuration controller when configuring using the Avalon® streaming x8 interface.
3'b001 or 3'b011 AS_DATA0 Connect this pin to the data0 pin of the QSPI flash device when configuring from the QSPI flash device.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO5 F[1,2]_SDM_IO5

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin will function as MSEL[0] during power up and reset to determine the configuration scheme. Once the pin completes the MSEL function, it will then function according to the configuration scheme you have selected.

For more information, refer to the Stratix® 10 Configuration User Guide .

— MSEL[0] This pin needs to be pulled-up to VCCIO_SDM or pulled-down to GND through a 4.7-kΩ resistor depending on your configuration scheme.
3'b001 or 3'b011 AS_nCSO0 Connect this pin to the nCS input of the first QSPI flash device when configuring from QSPI flash devices.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO6 F[1,2]_SDM_IO6

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

3'b110 AVSTx8_DATA4 Connect this pin to the data4 pin of an external configuration controller when configuring using the Avalon® streaming x8 interface.
3'b001 or 3'b011 AS_DATA3 Connect this pin to the data3 pin of the QSPI flash device when configuring from the QSPI flash device.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO7 F[1,2]_SDM_IO7

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin will function as MSEL[1] during power up and reset to determine the configuration scheme. Once the pin completes the MSEL function, it will then function according to the configuration scheme you have selected.

For more information, refer to the Stratix® 10 Configuration User Guide .

— MSEL[1] This pin needs to be pulled-up to VCCIO_SDM or pulled-down to GND through a 4.7-kΩ resistor depending on your configuration scheme.
3'b001 or 3'b011 AS_nCSO2 Connect this pin to the nCS input of the third QSPI flash device when you use cascaded QSPI flash devices for HPS application.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO8 F[1,2]_SDM_IO8

This pin is pulled low internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

3'b110 AVSTx8_READY Connect this pin to the ready signal output of the external configuration controller when configuring using the Avalon® streaming x8, x16, or x32 interface.
3'b001 or 3'b011 AS_nCSO3 Connect this pin to the nCS input of the fourth QSPI flash device when you use cascaded QSPI flash devices for HPS application.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO9 F[1,2]_SDM_IO9

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin will function as MSEL[2] during power up and reset to determine the configuration scheme. Once the pin completes the MSEL function, it will then function according to the configuration scheme you have selected.

For more information, refer to the Stratix® 10 Configuration User Guide .

— MSEL[2] This pin needs to be pulled-up to VCCIO_SDM or pulled-down to GND through a 4.7-kΩ resistor depending on your configuration scheme.
3'b001 or 3'b011 AS_nCSO1 Connect this pin to the nCS input of the second QSPI flash device when you use cascaded QSPI flash devices for HPS application.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO10 F[1,2]_SDM_IO10

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

3'b110 AVSTx8_DATA7 Connect this pin to the data7 pin of an external configuration controller when configuring using the Avalon® streaming x8 interface.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO11 F[1,2]_SDM_IO11

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

3'b110 AVSTx8_VALID Connect this pin to the data valid pin of an external configuration controller when configuring using the Avalon® streaming x8 interface.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO12 F[1,2]_SDM_IO12

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

— Any MSEL setting The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO13 F[1,2]_SDM_IO13

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

3'b110 AVSTx8_DATA5 Connect this pin to the data5 pin of an external configuration controller when configuring using the Avalon® streaming x8 interface.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO14 F[1,2]_SDM_IO14

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

3'b110 AVSTx8_CLK Connect this pin to the clock output of an external configuration controller when configuring using the Avalon® streaming x8 interface.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO15 F[1,2]_SDM_IO15

This pin is pulled high internally by a 25-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

3'b110 AVSTx8_DATA6 Connect this pin to the data6 pin of an external configuration controller when configuring using the Avalon® streaming x8 interface.
Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
SDM_IO16 F[1,2]_SDM_IO16

This pin is pulled low internally by a 25-kΩ resistor when the device is powered up.

Any valid MSEL setting Optional signals The connection guidelines for this pin has dependency on signal assignments. For more information, refer to the Secure Device Manager (SDM) Optional Signal Pins.
Level Two Title