Stratix® 10 Device Family Pin Connection Guidelines

Download PDF
ID 683028
Date 8/26/2024
Public
Document Table of Contents
Document Table of Contents x
Stratix® 10 Device Family Pin Connection Guidelines
Stratix® 10 Device Family Pin Connection Guidelines x
Stratix® 10 Core Pins Stratix® 10 High Bandwidth Memory (HBM) Pins H-Tile and L-Tile Pins Stratix® 10 E-Tile Pins Stratix® 10 P-Tile Pins Stratix® 10 Hard Processor System (HPS) Pins Power Supply Sharing Guidelines for Stratix® 10 Devices Document Revision History for the Stratix® 10 Device Family Pin Connection Guidelines
Stratix® 10 Core Pins x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins 3 V Compatible I/O Pins 3.3 V I/O Pins Differential I/O Pins External Memory Interface Pins Voltage Sensor Pins Temperature Sensor Pins Reference Pins No Connect and DNU Pins Power Supply Pins Secure Device Manager (SDM) Pins Secure Device Manager (SDM) Optional Signal Pins Notes to Stratix® 10 Core Pins
Stratix® 10 High Bandwidth Memory (HBM) Pins x
UIB and eSRAM Pins Stratix® 10 HBM Power Supply Pins Notes to Stratix® 10 HBM Pins
H-Tile and L-Tile Pins x
H-Tile and L-Tile Pins
Stratix® 10 E-Tile Pins x
Stratix® 10 E-Tile Pins Notes to Stratix® 10 E-Tile Pins
Stratix® 10 P-Tile Pins x
Stratix® 10 P-Tile Power Supply Pins Stratix® 10 P-Tile Transceiver Pins
Stratix® 10 Hard Processor System (HPS) Pins x
HPS Supply Pins HPS Oscillator Clock Input Pin HPS JTAG Pins HPS GPIO Pins HPS SDMMC Pins HPS NAND Pins HPS USB Pins HPS EMAC Pins HPS I2C_EMAC and MDIO Pins HPS I2C Pins HPS SPI Pins HPS UART Pins HPS Trace Pins Notes to Stratix® 10 HPS Pins
Power Supply Sharing Guidelines for Stratix® 10 Devices x
Example 1— Stratix® 10 GX Example 2— Stratix® 10 GX Example 3— Stratix® 10 GX (only for the HF35 Package) Example 4— Stratix® 10 GX (only for the HF35 Package) Example 5— Stratix® 10 SX (–1V, –2V, and –3V parts) Example 6— Stratix® 10 SX (–2L and –3X parts) Example 7— Stratix® 10 SX (–1V, –2V, and –3V parts) Example 8— Stratix® 10 SX (–2L and –3X parts) Example 9— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 10— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 11— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 12— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 13— Stratix® 10 MX (–1V, –2V, and –3V parts) Example 14— Stratix® 10 MX (–1V, –2V, and –3V parts) Example 15— Stratix® 10 MX (E-Tile) Example 16— Stratix® 10 TX (–1V, –2V, and –3V parts) Example 17— Stratix® 10 TX (–2L and –3X parts) Example 18— Stratix® 10 DX (–1V, –2V, and –3V parts) Example 19— Stratix® 10 GX 10M Example 20— Stratix® 10 GX 10M
Stratix® 10 Device Family Pin Connection Guidelines

H-Tile and L-Tile Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 17.  H-Tile and L-Tile Pins (See Notes 4 through 10)For more information about the pin description and connection guidelines of the nPERST[L,R][0:2] pins, refer to the Optional/Dual-Purpose Configuration Pins section. For more information about the pin description and connection guidelines of the OSC_CLK_1 pin, refer to the Dedicated Configuration/JTAG Pins section.
Pin Name ( Stratix® 10 Devices) Pin Name ( Stratix® 10 GX 10M Device) Pin Functions Pin Description Connection Guidelines
VCCR_GXB[L1,R4] [C,D,E,F,G,H,I,J,K,L,M,N]

VCCR_GXBL1[C,D,E]_T[1,3]

VCCR_GXBL1[K,L,M]_T[2,4]

Power

Analog power, receiver, specific to each transceiver bank of the left (L) side or right (R) side of the device.

Connect the VCCR_GXB pins to a 1.03-V or 1.12-V low noise switching regulator depending on the transceiver data rate.

The VCCR_GXB and VCCT_GXB pins of each bank within a transceiver tile (L-Tile or H-Tile) must have the same voltage (either 1.03 V or 1.12 V). However, VCCR_GXB and VCCT_GXB of different banks within the same transceiver tile can have different voltages based on the configured transceiver data rates to further reduce power consumption of the transceiver tile. When the banks within a transceiver tile are powered at different voltages (for example, some banks operating at 1.03 V while other banks operating at 1.12 V), the xN clock lines are only allowed to transverse between contiguous banks operating at the same VCCR_GXB or VCCT_GXB voltages. The xN clock lines crossing boundaries of banks operating at different voltages is not allowed. For any input reference clock coming into a transceiver tile, that clock can be distributed to any bank within the tile even if the VCCR_GXB and VCCT_GXB operating voltages of the banks are different.

When all of the transceivers on the same tile are not used, you may power down the transceivers in that tile by connecting its VCCR_GXB, VCCT_GXB, and VCCH_GXB to GND.

Place a 22-nF decoupling capacitor between each VCCR_GXB power pin and GND pin on the back side of the BGA pin field.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-Tile or H-Tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Stratix® 10 Device Datasheet.

See Notes 2, 3, 4, 7, and 10 in Notes to Stratix® 10 Core Pins.

VCCT_GXB[L1,R4] [C,D,E,F,G,H,I,J,K,L,M,N]

VCCT_GXBL1[C,D,E]_T[1,3]

VCCT_GXBL1[K,LM]_T[2,4]

Power Analog power, transmitter, specific to each transceiver bank of the left (L) side or right (R) side of the device.

Connect the VCCT_GXB pins to a 1.03-V or 1.12-V low noise switching regulator depending on the transceiver data rate.

The VCCR_GXB and VCCT_GXB pins of each bank within a transceiver tile (L-Tile or H-Tile) must have the same voltage (either 1.03 V or 1.12 V). However, VCCR_GXB and VCCT_GXB of different banks within the same transceiver tile can have different voltages based on the configured transceiver data rates to further reduce power consumption of the transceiver tile. When the banks within a transceiver tile are powered at different voltages (for example, some banks operating at 1.03 V while other banks operating at 1.12 V), the xN clock lines are only allowed to transverse between contiguous banks operating at the same VCCR_GXB or VCCT_GXB voltages. The xN clock lines crossing boundaries of banks operating at different voltages is not allowed. For any input reference clock coming into a transceiver tile, that clock can be distributed to any bank within the tile even if the VCCR_GXB and VCCT_GXB operating voltages of the banks are different.

When all of the transceivers on the same tile are not used, you may power down the transceivers in that tile by connecting its VCCR_GXB, VCCT_GXB, and VCCH_GXB to GND.

Place a 22-nF decoupling capacitor between each VCCT_GXB power pin and GND pin on the back side of the BGA pin field.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-Tile or H-Tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Stratix® 10 Device Datasheet.

See Notes 2, 3, 4, 7, and 10 in Notes to Stratix® 10 Core Pins.

VCCH_GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]

VCCH_GXBL1_T[1,3]

VCCH_GXBR1_T[2,4]

Power Analog power, block level transmitter buffers, specific to the left (L) side or right (R) side of the device.

Connect VCCH_GXB to 1.8-V low noise switching regulator.

With a proper isolation filtering, you have the option to source VCCH_GXB from the same regulator as VCCPT.

To minimize the regulator switching noise impact on channel jitter performance, keep the switching frequency for VCCH_GXB regulator below 2 MHz. For OTN applications, the switching frequency for VCCH_GXB is recommended to be below 500 KHz.

Place a 22-nF decoupling capacitor between each VCCH_GXB power pin and GND pin on the back side of the BGA pin field.

A leakage voltage may be observed on the VCCH_GXB power rail before the VCCH_GXB is powered on due to leakage inside the device during the power-up and power-down sequencing. The total magnitude of this leakage voltage is lower than VCCH_GXB and this is an expected behavior.

During the power-up sequence only, a transient current whose magnitude is less than the VCCH_GXB static operating current may be observed. The floating voltage and transient current are expected behavior and can neither cause any functional failure nor reliability concerns to the device provided that the power-up or power-down sequence is followed.

When all of the transceivers on the same tile are not used, you may power down the transceivers in that tile by connecting its VCCR_GXB, VCCT_GXB, and VCCH_GXB to GND.

See Notes 2, 3, 4, 7, and 10 in Notes to Stratix® 10 Core Pins.

GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_RX_CH[0:5]p

GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_REFCLK[0:5]p

T1_GXBL1[C,D,E,F]_RX_CH[0:5]P

T1_GXBL1[C,D,E,F]_REFCLK[0:5]p

T2_GXBL1[N,M,L,K]_RX_CH[0:5]P

T2_GXBL1[N,M,L,K]_REFCLK[0:5]p

T3_GXBL1[C,D,E,F]_RX_CH[0:5]P

T3_GXBL1[C,D,E,F]_REFCLK[0:5]p

T4_GXBL1[N,M,L,K]_RX_CH[0:5]P

T4_GXBL1[N,M,L,K]_REFCLK[0:5]p

Input High speed positive differential receiver channels or REFCLK inputs. Specific to each transceiver bank of the left (L) side or right (R) side of the device.

These pins can be AC-coupled or DC-coupled when used. For more information, refer to the transceiver specifications in the Stratix® 10 Device Datasheet .

Connect all unused GXB_RXp pins directly to GND.

GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_RX_CH[0:5]n

GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_REFCLK[0:5]n

T1_GXBL1[C,D,E,F]_RX_CH[0:5]n

T1_GXBL1[C,D,E,F]_REFCLK[0:5]n

T2_GXBL1[N,M,L,K]_RX_CH[0:5]n

T2_GXBL1[N,M,L,K]_REFCLK[0:5]n

T3_GXBL1[C,D,E,F]_RX_CH[0:5]n

T3_GXBL1[C,D,E,F]_REFCLK[0:5]n

T4_GXBL1[N,M,L,K]_RX_CH[0:5]n

T4_GXBL1[N,M,L,K]_REFCLK[0:5]n

Input High speed negative differential receiver channels or REFCLK inputs. Specific to each transceiver bank of the left (L) side or right (R) side of the device.

These pins can be AC-coupled or DC-coupled when used. For more information, refer to the transceiver specifications in the Stratix® 10 Device Datasheet .

Connect all unused GXB_RXn pins directly to GND.

GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_TX_CH[0:5]p

T1_GXBL1[C,D,E,F]_TX_CH[0:5]p

T2_GXBL1[N,M,L,K]_TX_CH[0:5]p

T3_GXBL1[C,D,E,F]_TX_CH[0:5]p

T4_GXBL1[N,M,L,K]_TX_CH[0:5]p

Output High speed positive differential transmitter channels. Specific to each transceiver bank of the left (L) side or right (R) side of the device. Leave all unused GXB_TXp pins floating.
GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_TX_CH[0:5]n

T1_GXBL1[C,D,E,F]_TX_CH[0:5]n

T2_GXBL1[N,M,L,K]_TX_CH[0:5]n

T3_GXBL1[C,D,E,F]_TX_CH[0:5]n

T4_GXBL1[N,M,L,K]_TX_CH[0:5]n

Output High speed negative differential transmitter channels. Specific to each transceiver bank of the left (L) side or right (R) side of the device. Leave all unused GXB_TXn pins floating.
REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_CH[B,T]p

T1_REFCLK_GXBL1[C,D,E,F]_CH[B,T]p

T2_REFCLK_GXBL1[N,M,L,K]_CH[B,T]p

T3_REFCLK_GXBL1[C,D,E,F]_CH[B,T]p

T4_REFCLK_GXBL1[N,M,L,K]_CH[B,T]p

Input

High speed differential reference clock positive receiver channels, specific to each transceiver bank of the left (L) side or right (R) side of the device.

REFCLK_GXB can be used as dedicated clock input pins with fPLL for core clock generation even when the transceiver channel is not used.

These pins should be AC-coupled when connected to any I/O standard other than the HCSL I/O standard. For the HCSL I/O standard, these pins must be DC-coupled. For example, PCIe* reference clocks should be DC-coupled if it uses the HCSL I/O standard.

Connect each unused REFCLK_GXB pin to GND plane directly on its own via. Do not share vias when connecting to GND.

The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration. For PCIe* , you must follow this clock requirement.

See Note 9 in Notes to Stratix® 10 Core Pins.

REFCLK_GXB[L1,R4][C,D,E,F,G,H,I,J,K,L,M,N]_CH[B,T]n

T1_REFCLK_GXBL1[C,D,E,F]_CH[B,T]n

T2_REFCLK_GXBL1[N,M,L,K]_CH[B,T]n

T3_REFCLK_GXBL1[C,D,E,F]_CH[B,T]n

T4_REFCLK_GXBL1[N,M,L,K]_CH[B,T]n

Input

High speed differential reference clock complement, complementary receiver channel, specific to each transceiver bank of the left (L) side or right (R) side of the device.

REFCLK_GXB can be used as dedicated clock input pins with fPLL for core clock generation even when the transceiver channel is not used.

These pins should be AC-coupled when connected to any I/O standard other than the HCSL I/O standard. For the HCSL I/O standard, these pins must be DC-coupled. For example, PCIe* reference clocks should be DC-coupled if it uses the HCSL I/O standard.

Connect each unused REFCLK_GXB pin to GND plane directly on its own via. Do not share vias when connecting to GND.

The input reference clock must be stable and free-running at device power-up for proper PLL calibrations and a successful configuration. For PCIe* , you must follow this clock requirement.

See Note 9 in Notes to Stratix® 10 Core Pins.

RREF_[T,M,B][L,R]

T1_RREF_BL

T2_RREF_BR

T3_RREF_BL

T4_RREF_BR

Input Reference resistor for fPLL, IOPLL, and transceiver, specific to the top (T), middle (M), and bottom (B) of the left (L) side or right (R) side of the device.

If any REFCLK pin or transceiver channel on one side (left or right) of the device, IOPLL, or fPLL is used, you must connect each RREF pin on that side of the device to its own individual 2 kΩ ±1% resistor to GND.

Otherwise, you can connect each RREF pin on that side of the device directly to GND. In the PCB layout, the trace from this pin to the resistor needs to be routed so that it avoids any aggressor signals.

RREF_SIPAUX0 — Input Reference resistor pin for UIB PLL.

You must connect the RREF_SIPAUX0 pin to a 2 kΩ ±1% resistor to GND.

In the PCB layout, the trace from this pin to the resistor must be routed so that it avoids any aggressor signals.

Table 18.  Physical Mapping of the Transceiver Channel Corresponding to the 3V I/O Bank
H-Tile/L-Tile Bank
1C, 1D, 1E, 1F 1K, 1L, 1M, 1N 4C, 4D, 4E, 4F 4K, 4L, 4M, 4N
3VIO pins IO3V[0..7]_10 IO3V[0..7]_12 IO3V[0..7]_20 IO3V[0..7]_22
Level Two Title