Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 12/19/2024
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Document Table of Contents x
1. Stratix® 10 Device Family Pin Connection Guidelines
1. Stratix® 10 Device Family Pin Connection Guidelines x
1.1. Stratix® 10 Core Pins 1.2. Stratix® 10 High Bandwidth Memory (HBM) Pins 1.3. H-Tile and L-Tile Pins 1.4. Stratix® 10 E-Tile Pins 1.5. Stratix® 10 P-Tile Pins 1.6. Stratix® 10 Hard Processor System (HPS) Pins 1.7. Power Supply Sharing Guidelines for Stratix® 10 Devices 1.8. Document Revision History for the Stratix® 10 Device Family Pin Connection Guidelines
1.1. Stratix® 10 Core Pins x
1.1.1. Clock and PLL Pins 1.1.2. Dedicated Configuration/JTAG Pins 1.1.3. Optional/Dual-Purpose Configuration Pins 1.1.4. 3 V Compatible I/O Pins 1.1.5. 3.3 V I/O Pins 1.1.6. Differential I/O Pins 1.1.7. External Memory Interface Pins 1.1.8. Voltage Sensor Pins 1.1.9. Temperature Sensor Pins 1.1.10. Reference Pins 1.1.11. No Connect and DNU Pins 1.1.12. Power Supply Pins 1.1.13. Secure Device Manager (SDM) Pins 1.1.14. Secure Device Manager (SDM) Optional Signal Pins 1.1.15. Notes to Stratix® 10 Core Pins
1.2. Stratix® 10 High Bandwidth Memory (HBM) Pins x
1.2.1. UIB and eSRAM Pins 1.2.2. Stratix® 10 HBM Power Supply Pins 1.2.3. Notes to Stratix® 10 HBM Pins
1.3. H-Tile and L-Tile Pins x
1.3.1. H-Tile and L-Tile Pins
1.4. Stratix® 10 E-Tile Pins x
1.4.1. Stratix® 10 E-Tile Pins 1.4.2. Notes to Stratix® 10 E-Tile Pins
1.5. Stratix® 10 P-Tile Pins x
1.5.1. Stratix® 10 P-Tile Power Supply Pins 1.5.2. Stratix® 10 P-Tile Transceiver Pins
1.6. Stratix® 10 Hard Processor System (HPS) Pins x
1.6.1. HPS Supply Pins 1.6.2. HPS Oscillator Clock Input Pin 1.6.3. HPS JTAG Pins 1.6.4. HPS GPIO Pins 1.6.5. HPS SDMMC Pins 1.6.6. HPS NAND Pins 1.6.7. HPS USB Pins 1.6.8. HPS EMAC Pins 1.6.9. HPS I2C_EMAC and MDIO Pins 1.6.10. HPS I2C Pins 1.6.11. HPS SPI Pins 1.6.12. HPS UART Pins 1.6.13. HPS Trace Pins 1.6.14. Notes to Stratix® 10 HPS Pins
1.7. Power Supply Sharing Guidelines for Stratix® 10 Devices x
1.7.1. Example 1— Stratix® 10 GX 1.7.2. Example 2— Stratix® 10 GX 1.7.3. Example 3— Stratix® 10 GX (only for the HF35 Package) 1.7.4. Example 4— Stratix® 10 GX (only for the HF35 Package) 1.7.5. Example 5— Stratix® 10 SX (–1V, –2V, and –3V parts) 1.7.6. Example 6— Stratix® 10 SX (–2L and –3X parts) 1.7.7. Example 7— Stratix® 10 SX (–1V, –2V, and –3V parts) 1.7.8. Example 8— Stratix® 10 SX (–2L and –3X parts) 1.7.9. Example 9— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) 1.7.10. Example 10— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) 1.7.11. Example 11— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) 1.7.12. Example 12— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) 1.7.13. Example 13— Stratix® 10 MX (–1V, –2V, and –3V parts) 1.7.14. Example 14— Stratix® 10 MX (–1V, –2V, and –3V parts) 1.7.15. Example 15— Stratix® 10 MX (E-Tile) 1.7.16. Example 16— Stratix® 10 TX (–1V, –2V, and –3V parts) 1.7.17. Example 17— Stratix® 10 TX (–2L and –3X parts) 1.7.18. Example 18— Stratix® 10 DX (–1V, –2V, and –3V parts) 1.7.19. Example 19— Stratix® 10 GX 10M 1.7.20. Example 20— Stratix® 10 GX 10M
1. Stratix® 10 Device Family Pin Connection Guidelines

1.6.8. HPS EMAC Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 29.  HPS EMAC PinsThere are three EMAC controllers (EMAC0, EMAC1, and EMAC2) for the Stratix® 10 HPS.
HPS Pin Function Pin Description and Connection Guidelines Pin Type Valid Assignments
EMAC0_TX_CLK EMAC0 Transmit Clock Output HPS_IOA_13
EMAC0_TX_CTL EMAC0 Transmit Control Output HPS_IOA_14
EMAC0_RX_CLK EMAC0 Receive Clock Input HPS_IOA_15
EMAC0_RX_CTL EMAC0 Receive Control Input HPS_IOA_16
EMAC0_TXD0 EMAC0 Transmit Data Bit 0 Output HPS_IOA_17
EMAC0_TXD1 EMAC0 Transmit Data Bit 1 Output HPS_IOA_18
EMAC0_RXD0 EMAC0 Receive Data Bit 0 Input HPS_IOA_19
EMAC0_RXD1 EMAC0 Receive Data Bit 1 Input HPS_IOA_20
EMAC0_TXD2 EMAC0 Transmit Data Bit 2 Output HPS_IOA_21
EMAC0_TXD3 EMAC0 Transmit Data Bit 3 Output HPS_IOA_22
EMAC0_RXD2 EMAC0 Receive Data Bit 2 Input HPS_IOA_23
EMAC0_RXD3 EMAC0 Receive Data Bit 3 Input HPS_IOA_24
EMAC1_TX_CLK EMAC1 Transmit Clock Output HPS_IOB_1
EMAC1_TX_CTL EMAC1 Transmit Control Output HPS_IOB_2
EMAC1_RX_CLK EMAC1 Receive Clock Input HPS_IOB_3
EMAC1_RX_CTL EMAC1 Receive Control. Input HPS_IOB_4
EMAC1_TXD0 EMAC1 Transmit Data Bit 0 Output HPS_IOB_5
EMAC1_TXD1 EMAC1 Transmit Data Bit 1 Output HPS_IOB_6
EMAC1_RXD0 EMAC1 Receive Data Bit 0 Input HPS_IOB_7
EMAC1_RXD1 EMAC1 Receive Data Bit 1 Input HPS_IOB_8
EMAC1_TXD2 EMAC1 Transmit Data Bit 2 Output HPS_IOB_9
EMAC1_TXD3 EMAC1 Transmit Data Bit 3 Output HPS_IOB_10
EMAC1_RXD2 EMAC1 Receive Data Bit 2 Input HPS_IOB_11
EMAC1_RXD3 EMAC1 Receive Data Bit 3 Input HPS_IOB_12
EMAC2_TX_CLK EMAC2 Transmit Clock Output HPS_IOB_13
EMAC2_TX_CTL EMAC2 Transmit Control Output HPS_IOB_14
EMAC2_RX_CLK EMAC2 Receive Clock Input HPS_IOB_15
EMAC2_RX_CTL EMAC2 Receive Control Input HPS_IOB_16
EMAC2_TXD0 EMAC2 Transmit Data Bit 0 Output HPS_IOB_17
EMAC2_TXD1 EMAC2 Transmit Data Bit 1 Output HPS_IOB_18
EMAC2_RXD0 EMAC2 Receive Data Bit 0 Input HPS_IOB_19
EMAC2_RXD1 EMAC2 Receive Data Bit 1 Input HPS_IOB_20
EMAC2_TXD2 EMAC2 Transmit Data Bit 2 Output HPS_IOB_21
EMAC2_TXD3 EMAC2 Transmit Data Bit 3 Output HPS_IOB_22
EMAC2_RXD2 EMAC2 Receive Data Bit 2 Input HPS_IOB_23
EMAC2_RXD3 EMAC2 Receive Data Bit 3 Input HPS_IOB_24
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