Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 12/19/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 Device Family Pin Connection Guidelines
1. Stratix® 10 Device Family Pin Connection Guidelines x
1.1. Stratix® 10 Core Pins 1.2. Stratix® 10 High Bandwidth Memory (HBM) Pins 1.3. H-Tile and L-Tile Pins 1.4. Stratix® 10 E-Tile Pins 1.5. Stratix® 10 P-Tile Pins 1.6. Stratix® 10 Hard Processor System (HPS) Pins 1.7. Power Supply Sharing Guidelines for Stratix® 10 Devices 1.8. Document Revision History for the Stratix® 10 Device Family Pin Connection Guidelines
1.1. Stratix® 10 Core Pins x
1.1.1. Clock and PLL Pins 1.1.2. Dedicated Configuration/JTAG Pins 1.1.3. Optional/Dual-Purpose Configuration Pins 1.1.4. 3 V Compatible I/O Pins 1.1.5. 3.3 V I/O Pins 1.1.6. Differential I/O Pins 1.1.7. External Memory Interface Pins 1.1.8. Voltage Sensor Pins 1.1.9. Temperature Sensor Pins 1.1.10. Reference Pins 1.1.11. No Connect and DNU Pins 1.1.12. Power Supply Pins 1.1.13. Secure Device Manager (SDM) Pins 1.1.14. Secure Device Manager (SDM) Optional Signal Pins 1.1.15. Notes to Stratix® 10 Core Pins
1.2. Stratix® 10 High Bandwidth Memory (HBM) Pins x
1.2.1. UIB and eSRAM Pins 1.2.2. Stratix® 10 HBM Power Supply Pins 1.2.3. Notes to Stratix® 10 HBM Pins
1.3. H-Tile and L-Tile Pins x
1.3.1. H-Tile and L-Tile Pins
1.4. Stratix® 10 E-Tile Pins x
1.4.1. Stratix® 10 E-Tile Pins 1.4.2. Notes to Stratix® 10 E-Tile Pins
1.5. Stratix® 10 P-Tile Pins x
1.5.1. Stratix® 10 P-Tile Power Supply Pins 1.5.2. Stratix® 10 P-Tile Transceiver Pins
1.6. Stratix® 10 Hard Processor System (HPS) Pins x
1.6.1. HPS Supply Pins 1.6.2. HPS Oscillator Clock Input Pin 1.6.3. HPS JTAG Pins 1.6.4. HPS GPIO Pins 1.6.5. HPS SDMMC Pins 1.6.6. HPS NAND Pins 1.6.7. HPS USB Pins 1.6.8. HPS EMAC Pins 1.6.9. HPS I2C_EMAC and MDIO Pins 1.6.10. HPS I2C Pins 1.6.11. HPS SPI Pins 1.6.12. HPS UART Pins 1.6.13. HPS Trace Pins 1.6.14. Notes to Stratix® 10 HPS Pins
1.7. Power Supply Sharing Guidelines for Stratix® 10 Devices x
1.7.1. Example 1— Stratix® 10 GX 1.7.2. Example 2— Stratix® 10 GX 1.7.3. Example 3— Stratix® 10 GX (only for the HF35 Package) 1.7.4. Example 4— Stratix® 10 GX (only for the HF35 Package) 1.7.5. Example 5— Stratix® 10 SX (–1V, –2V, and –3V parts) 1.7.6. Example 6— Stratix® 10 SX (–2L and –3X parts) 1.7.7. Example 7— Stratix® 10 SX (–1V, –2V, and –3V parts) 1.7.8. Example 8— Stratix® 10 SX (–2L and –3X parts) 1.7.9. Example 9— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) 1.7.10. Example 10— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) 1.7.11. Example 11— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) 1.7.12. Example 12— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) 1.7.13. Example 13— Stratix® 10 MX (–1V, –2V, and –3V parts) 1.7.14. Example 14— Stratix® 10 MX (–1V, –2V, and –3V parts) 1.7.15. Example 15— Stratix® 10 MX (E-Tile) 1.7.16. Example 16— Stratix® 10 TX (–1V, –2V, and –3V parts) 1.7.17. Example 17— Stratix® 10 TX (–2L and –3X parts) 1.7.18. Example 18— Stratix® 10 DX (–1V, –2V, and –3V parts) 1.7.19. Example 19— Stratix® 10 GX 10M 1.7.20. Example 20— Stratix® 10 GX 10M
1. Stratix® 10 Device Family Pin Connection Guidelines

1.1.1. Clock and PLL Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 1.  Clock and PLL Pins
Pin Name ( Stratix® 10 Devices) Pin Name ( Stratix® 10 GX 10M Device) Pin Functions Pin Description Connection Guidelines

CLK_[2][A,B,C,F,G,H,I,J,K,L,M,N]_[0,1]p

CLK_[3][A,B,C,D,E,F,G,H,I,J,K,L]_[0,1]p

CLK_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_[0,1]p

CLK_[3] [A,B,C,D,E,F,G,H,I,J,K,L]U[1,2]_[0,1]p

I/O, Clock Input

Dedicated high speed clock input pins that can be used for data inputs or outputs. Differential input OCT Rd, single-ended input OCT Rt, and single-ended output OCT Rs are supported on these pins.

When you do not use these pins as dedicated clock pins, you can use them as regular I/O pins.

Tie the unused pins to GND or leave them unconnected. If the pins are not connected, use the Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak internal pull-up resistor enabled, or as outputs driving GND.

CLK_[2][A,B,C,F,G,H,I,J,K,L,M,N]_[0,1]n

CLK_[3][A,B,C,D,E,F,G,H,I,J,K,L]_[0,1]n

CLK_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_[0,1]n

CLK_[3] [A,B,C,D,E,F,G,H,I,J,K,L]U[1,2]_[0,1]n

I/O, Clock Input

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_FB[0]

PLL_[3][A,B,C,F,G,H,I,J,K,L]_FB[0]

PLL_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_FB[0,1]

PLL_[3] [A,B,C,D,E,F,G,H,I,J,K,L]_U[1,2]_FB[0,1]

I/O, Clock

Dual-purpose I/O pins that can be used as single-ended inputs, single-ended outputs, or external feedback input pins.

For more information about the supported pins, refer to the device pin-out file.

Tie the unused pins to GND or leave them unconnected. If the pins are not connected, use the Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak internal pull-up resistor enabled, or as outputs driving GND.

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_FBp

PLL_[3][A,B,C,F,G,H,I,J,K,L]_FBp

— I/O, Clock

Dual-purpose I/O pins that can be used as differential I/Os, or external feedback input pins.

For more information about the supported pins, refer to the device pin-out file.

Tie the unused pins to GND or leave them unconnected. If the pins are not connected, use the Quartus® Prime software programmable options to internally bias these pins.

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_FBn

PLL_[3][A,B,C,F,G,H,I,J,K,L]_FBn

— I/O, Clock

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_CLKOUT[0:1]

PLL_[3][A,B,C,F,G,H,I,J,K,L]_CLKOUT[0:1]

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_CLKOUT[0:1]p

PLL_[3][A,B,C,F,G,H,I,J,K,L]_CLKOUT[0:1]p

PLL_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_CLKOUT[0:1]

PLL_[3] [A,B,C,D,E,F,G,H,I,J,K,L]_U[1,2]_CLKOUT[0:1]

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_CLKOUT[0:1]p

PLL_[2] [A,B,C,D,E,F,G,H,I,J,K,L]U[1,2]_CLKOUT[0:1]p 		I/O, Clock

I/O pins that can be used as two single-ended clock output pins or one differential clock output pair.

For more information about the supported pins, refer to the device pin-out file.

Tie the unused pins to GND or leave them unconnected. If the pins are not connected, use the Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak internal pull-up resistor enabled, or as outputs driving GND.

PLL_[2][A,B,C,F,G,H,I,J,K,L,M,N]_CLKOUT[0:1]n

PLL_[3][A,B,C,F,G,H,I,J,K,L]_CLKOUT[0:1]n

PLL_[2] [A,B,C,F,G,H,I,J,K,L,M,N]U[1,2]_CLKOUT[0:1]n

PLL_[3] [A,B,C,D,E,F,G,H,I,J,K,L]U[1,2]_CLKOUT[0:1]n

I/O, Clock
Level Two Title