Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 12/19/2024
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Document Table of Contents x
1. Stratix® 10 Device Family Pin Connection Guidelines
1. Stratix® 10 Device Family Pin Connection Guidelines x
1.1. Stratix® 10 Core Pins 1.2. Stratix® 10 High Bandwidth Memory (HBM) Pins 1.3. H-Tile and L-Tile Pins 1.4. Stratix® 10 E-Tile Pins 1.5. Stratix® 10 P-Tile Pins 1.6. Stratix® 10 Hard Processor System (HPS) Pins 1.7. Power Supply Sharing Guidelines for Stratix® 10 Devices 1.8. Document Revision History for the Stratix® 10 Device Family Pin Connection Guidelines
1.1. Stratix® 10 Core Pins x
1.1.1. Clock and PLL Pins 1.1.2. Dedicated Configuration/JTAG Pins 1.1.3. Optional/Dual-Purpose Configuration Pins 1.1.4. 3 V Compatible I/O Pins 1.1.5. 3.3 V I/O Pins 1.1.6. Differential I/O Pins 1.1.7. External Memory Interface Pins 1.1.8. Voltage Sensor Pins 1.1.9. Temperature Sensor Pins 1.1.10. Reference Pins 1.1.11. No Connect and DNU Pins 1.1.12. Power Supply Pins 1.1.13. Secure Device Manager (SDM) Pins 1.1.14. Secure Device Manager (SDM) Optional Signal Pins 1.1.15. Notes to Stratix® 10 Core Pins
1.2. Stratix® 10 High Bandwidth Memory (HBM) Pins x
1.2.1. UIB and eSRAM Pins 1.2.2. Stratix® 10 HBM Power Supply Pins 1.2.3. Notes to Stratix® 10 HBM Pins
1.3. H-Tile and L-Tile Pins x
1.3.1. H-Tile and L-Tile Pins
1.4. Stratix® 10 E-Tile Pins x
1.4.1. Stratix® 10 E-Tile Pins 1.4.2. Notes to Stratix® 10 E-Tile Pins
1.5. Stratix® 10 P-Tile Pins x
1.5.1. Stratix® 10 P-Tile Power Supply Pins 1.5.2. Stratix® 10 P-Tile Transceiver Pins
1.6. Stratix® 10 Hard Processor System (HPS) Pins x
1.6.1. HPS Supply Pins 1.6.2. HPS Oscillator Clock Input Pin 1.6.3. HPS JTAG Pins 1.6.4. HPS GPIO Pins 1.6.5. HPS SDMMC Pins 1.6.6. HPS NAND Pins 1.6.7. HPS USB Pins 1.6.8. HPS EMAC Pins 1.6.9. HPS I2C_EMAC and MDIO Pins 1.6.10. HPS I2C Pins 1.6.11. HPS SPI Pins 1.6.12. HPS UART Pins 1.6.13. HPS Trace Pins 1.6.14. Notes to Stratix® 10 HPS Pins
1.7. Power Supply Sharing Guidelines for Stratix® 10 Devices x
1.7.1. Example 1— Stratix® 10 GX 1.7.2. Example 2— Stratix® 10 GX 1.7.3. Example 3— Stratix® 10 GX (only for the HF35 Package) 1.7.4. Example 4— Stratix® 10 GX (only for the HF35 Package) 1.7.5. Example 5— Stratix® 10 SX (–1V, –2V, and –3V parts) 1.7.6. Example 6— Stratix® 10 SX (–2L and –3X parts) 1.7.7. Example 7— Stratix® 10 SX (–1V, –2V, and –3V parts) 1.7.8. Example 8— Stratix® 10 SX (–2L and –3X parts) 1.7.9. Example 9— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) 1.7.10. Example 10— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) 1.7.11. Example 11— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) 1.7.12. Example 12— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) 1.7.13. Example 13— Stratix® 10 MX (–1V, –2V, and –3V parts) 1.7.14. Example 14— Stratix® 10 MX (–1V, –2V, and –3V parts) 1.7.15. Example 15— Stratix® 10 MX (E-Tile) 1.7.16. Example 16— Stratix® 10 TX (–1V, –2V, and –3V parts) 1.7.17. Example 17— Stratix® 10 TX (–2L and –3X parts) 1.7.18. Example 18— Stratix® 10 DX (–1V, –2V, and –3V parts) 1.7.19. Example 19— Stratix® 10 GX 10M 1.7.20. Example 20— Stratix® 10 GX 10M
1. Stratix® 10 Device Family Pin Connection Guidelines

1.7.7. Example 7— Stratix® 10 SX (–1V, –2V, and –3V parts)

Table 41.  Power Supply Sharing Guidelines for Stratix® 10 SX (–1V, –2V, and –3V parts) with 15 Gbps < Transceiver Data Rate <= 28.3 GbpsExample Requiring 6 Power Regulators
Power Pin Name Regulator Group Voltage Level (V) Supply Tolerance Power Source Regulator Sharing Notes
VCC 1

SmartVID

 ±30 mV Switcher 13 Share

Source VCC and VCCP from the same regulator, sharing the same voltage plane. You have the option to connect VCCL_HPS to the same regulator as VCC and VCCP when the power rails require the same voltage level. You may also connect the VCCPLLDIG_HPS power to the shared VCC, VCCP, and VCCL_HPS power planes with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS and VCCPLLDIG_HPS floating or connect them to GND.

VCCP
VCCL_HPS
VCCPLLDIG_HPS Filter
VCCERAM 2 0.9 ±30 mV Switcher13 Isolate

Connect the VCCERAM to a dedicated 0.9 V power supply. You may connect the VCCPLLDIG_SDM power to the VCCERAM power plane with proper isolation filtering.

When implementing a filtered supply topology, you must consider the IR drop across the filter.
VCCPLLDIG_SDM Filter
VCCR_GXB[L,R] 3 1.12 ±20 mV Switcher13 Isolate

Connect the VCCR_GXB to a dedicated 1.12 V power supply.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-Tile or H-Tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Stratix® 10 Device Datasheet.

VCCT_GXB[L,R] 4 1.12 ±20 mV Switcher13 Isolate

Connect the VCCT_GXB to a dedicated 1.12 V power supply.

The VCCR_GXB and VCCT_GXB voltage supplies can vary depending on whether it is an L-Tile or H-Tile device as well as the channel configuration (non-bonded versus bonded channels) on each tile. For more information about the voltage requirement for your specific use case, refer to the Stratix® 10 Device Datasheet.

VCCPT 5 1.8 ±5% 14 Switcher13 Share if 1.8 V

You may source VCCPT and VCCIO_SDM from the same regulator. You may connect the VCCIO, VCCIO3V, VCCIO_HPS, and VCCBAT to the same power plane if the those power rails are at the same voltage level. You may also connect the VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Stratix® 10 devices.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

If you do not intend to utilize the HPS in the Stratix® 10 SX device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS and VCCPLL_HPS floating or connect them to GND.

VCCIO_SDM 1.8
VCCIO Varies
VCCIO3V Varies
VCCIO_HPS 1.8
VCCBAT Varies
VCCH_GXB[L,R] 1.8 Filter
VCCA_PLL 1.8
VCCPLL_SDM 1.8
VCCPLL_HPS 1.8
VCCADC 1.8
VCCFUSEWR_SDM 6 2.4 ±50 mV Switcher13 Isolate Connect VCCFUSEWR_SDM to a dedicated 2.4 V power supply if the SDM fuses need to be written. Leave VCCFUSEWR_SDM unconnected or tie it to VCCPT 1.8 V power if the SDM fuses do not need to be written. Do not tie this pin to GND.

Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Stratix® 10 SX device is provided in the following figure.

Figure 7. Example Power Supply Sharing Guidelines for Stratix® 10 SX (–1V, –2V, and –3V parts) with 15 Gbps < Transceiver Data Rate <= 28.3 Gbps
13 When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined as defined in note 7 of the Notes to Stratix® 10 Core Pins.
14 The supported tolerance for the VCCIO power supply varies depending on the I/O standards. For more details, refer to the I/O standard specification in the Stratix® 10 Device Datasheet. Use the EPE (Early Power Estimator) or Power and Thermal Calculator (PTC), and the Quartus® Prime Power Analyzer tool to assist in determining the power required for your specific design.
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