Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 8/26/2024
Public
Document Table of Contents
Document Table of Contents x
Stratix® 10 Device Family Pin Connection Guidelines
Stratix® 10 Device Family Pin Connection Guidelines x
Stratix® 10 Core Pins Stratix® 10 High Bandwidth Memory (HBM) Pins H-Tile and L-Tile Pins Stratix® 10 E-Tile Pins Stratix® 10 P-Tile Pins Stratix® 10 Hard Processor System (HPS) Pins Power Supply Sharing Guidelines for Stratix® 10 Devices Document Revision History for the Stratix® 10 Device Family Pin Connection Guidelines
Stratix® 10 Core Pins x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins 3 V Compatible I/O Pins 3.3 V I/O Pins Differential I/O Pins External Memory Interface Pins Voltage Sensor Pins Temperature Sensor Pins Reference Pins No Connect and DNU Pins Power Supply Pins Secure Device Manager (SDM) Pins Secure Device Manager (SDM) Optional Signal Pins Notes to Stratix® 10 Core Pins
Stratix® 10 High Bandwidth Memory (HBM) Pins x
UIB and eSRAM Pins Stratix® 10 HBM Power Supply Pins Notes to Stratix® 10 HBM Pins
H-Tile and L-Tile Pins x
H-Tile and L-Tile Pins
Stratix® 10 E-Tile Pins x
Stratix® 10 E-Tile Pins Notes to Stratix® 10 E-Tile Pins
Stratix® 10 P-Tile Pins x
Stratix® 10 P-Tile Power Supply Pins Stratix® 10 P-Tile Transceiver Pins
Stratix® 10 Hard Processor System (HPS) Pins x
HPS Supply Pins HPS Oscillator Clock Input Pin HPS JTAG Pins HPS GPIO Pins HPS SDMMC Pins HPS NAND Pins HPS USB Pins HPS EMAC Pins HPS I2C_EMAC and MDIO Pins HPS I2C Pins HPS SPI Pins HPS UART Pins HPS Trace Pins Notes to Stratix® 10 HPS Pins
Power Supply Sharing Guidelines for Stratix® 10 Devices x
Example 1— Stratix® 10 GX Example 2— Stratix® 10 GX Example 3— Stratix® 10 GX (only for the HF35 Package) Example 4— Stratix® 10 GX (only for the HF35 Package) Example 5— Stratix® 10 SX (–1V, –2V, and –3V parts) Example 6— Stratix® 10 SX (–2L and –3X parts) Example 7— Stratix® 10 SX (–1V, –2V, and –3V parts) Example 8— Stratix® 10 SX (–2L and –3X parts) Example 9— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 10— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 11— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 12— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 13— Stratix® 10 MX (–1V, –2V, and –3V parts) Example 14— Stratix® 10 MX (–1V, –2V, and –3V parts) Example 15— Stratix® 10 MX (E-Tile) Example 16— Stratix® 10 TX (–1V, –2V, and –3V parts) Example 17— Stratix® 10 TX (–2L and –3X parts) Example 18— Stratix® 10 DX (–1V, –2V, and –3V parts) Example 19— Stratix® 10 GX 10M Example 20— Stratix® 10 GX 10M
Stratix® 10 Device Family Pin Connection Guidelines

Optional/Dual-Purpose Configuration Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 3.  Optional/Dual-Purpose Configuration Pins
Pin Name ( Stratix® 10 Devices) Pin Name ( Stratix® 10 GX 10M Device) Pin Functions Pin Description Connection Guidelines
AVST_DATA[31:0] — I/O, Input

Dual-purpose configuration data input pins.

Use DATA [15:0] pins for Avalon® streaming interface x16 mode, DATA [31:0] pins for Avalon® streaming interface x32 mode, or as regular I/O pins.

Avalon® streaming interface x8 mode uses the SDM_IO pins.

These pins can also be used as user I/O pins after configuration.

If these pins are not used as the dual-purpose pins and they are not used as I/O pins, leave these pins unconnected.
AVST_CLK — I/O, Input

Dual-purpose Avalon® streaming interface clock input pin.

This pin is used for Avalon® streaming interface x16 and x32 configuration schemes.

This pin can also be used as a user I/O pin after configuration.

Connect this pin to the clock signal of an external configuration controller when configuring using the Avalon® streaming x16 or x32 interface.
AVST_VALID — I/O, Input

Dual-purpose Avalon® streaming interface data valid input pin.

This pin is used for Avalon® streaming interface x16 and x32 configuration schemes.

This pin can also be used as a user I/O pin after configuration.

Connect this pin to the data valid signal of an external configuration controller when configuring using the Avalon® streaming x16 or x32 interface.
nPERST[L,R][0:2] nPERST[L,R][0:2] I/O, Input

Dual-purpose fundamental reset pin that is only available when you use together with PCI Express® (PCIe®) hard IP (HIP).

When the PCIe* HIP on a side (left or right) is enabled, the nPERST pins on that side cannot be used as general-purpose I/Os (GPIOs). In this case, connect the nPERST pin to the system PCIe* nPERST signal to ensure that both ends of the link start link-training at the same time. The nPERST pins on a side are available as GPIOs only when the PCIe* HIP on that side is not enabled.

When the pin is low, the transceivers are in reset. When the pin is high, the transceivers are out of reset. When you do not use this pin as the fundamental reset, you can use this pin as a user I/O pin.

Connect this pin as defined in the Quartus® Prime software. This pin is powered by the VCCIO3V supply.

When VCCIO3V is connected to a 3.0-V supply, you must use a diode to clamp the 3.3 V LVTTL PCIe* input signal to the VCCIO3V power of the device.

When VCCIO3V is connected to any voltage other than 3.0 V, you must use a level translator to shift down the voltage from 3.3 V LVTTL to the corresponding voltage level powering the VCCIO3V pin.

Only one nPERST pin is used per PCIe* HIP. The Stratix® 10 components may have all six pins listed even when the specific component might only have 1 or 2 PCIe* HIPs.
  • nPERSTL0 = Bottom Left PCIe* HIP & CvP
  • nPERSTL1 = Middle Left PCIe* HIP (When available)
  • nPERSTL2 = Top Left PCIe* HIP (When available)
  • nPERSTR0 = Bottom Right PCIe* HIP (When available)
  • nPERSTR1 = Middle Right PCIe* HIP (When available)
  • nPERSTR2 = Top Right PCIe* HIP (When available)

For maximum compatibility, always use the bottom left PCIe* HIP first, as this is the only location that supports Configuration via Protocol (CvP) using the PCIe* link.

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