Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 8/26/2024
Public
Document Table of Contents
Document Table of Contents x
Stratix® 10 Device Family Pin Connection Guidelines
Stratix® 10 Device Family Pin Connection Guidelines x
Stratix® 10 Core Pins Stratix® 10 High Bandwidth Memory (HBM) Pins H-Tile and L-Tile Pins Stratix® 10 E-Tile Pins Stratix® 10 P-Tile Pins Stratix® 10 Hard Processor System (HPS) Pins Power Supply Sharing Guidelines for Stratix® 10 Devices Document Revision History for the Stratix® 10 Device Family Pin Connection Guidelines
Stratix® 10 Core Pins x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins 3 V Compatible I/O Pins 3.3 V I/O Pins Differential I/O Pins External Memory Interface Pins Voltage Sensor Pins Temperature Sensor Pins Reference Pins No Connect and DNU Pins Power Supply Pins Secure Device Manager (SDM) Pins Secure Device Manager (SDM) Optional Signal Pins Notes to Stratix® 10 Core Pins
Stratix® 10 High Bandwidth Memory (HBM) Pins x
UIB and eSRAM Pins Stratix® 10 HBM Power Supply Pins Notes to Stratix® 10 HBM Pins
H-Tile and L-Tile Pins x
H-Tile and L-Tile Pins
Stratix® 10 E-Tile Pins x
Stratix® 10 E-Tile Pins Notes to Stratix® 10 E-Tile Pins
Stratix® 10 P-Tile Pins x
Stratix® 10 P-Tile Power Supply Pins Stratix® 10 P-Tile Transceiver Pins
Stratix® 10 Hard Processor System (HPS) Pins x
HPS Supply Pins HPS Oscillator Clock Input Pin HPS JTAG Pins HPS GPIO Pins HPS SDMMC Pins HPS NAND Pins HPS USB Pins HPS EMAC Pins HPS I2C_EMAC and MDIO Pins HPS I2C Pins HPS SPI Pins HPS UART Pins HPS Trace Pins Notes to Stratix® 10 HPS Pins
Power Supply Sharing Guidelines for Stratix® 10 Devices x
Example 1— Stratix® 10 GX Example 2— Stratix® 10 GX Example 3— Stratix® 10 GX (only for the HF35 Package) Example 4— Stratix® 10 GX (only for the HF35 Package) Example 5— Stratix® 10 SX (–1V, –2V, and –3V parts) Example 6— Stratix® 10 SX (–2L and –3X parts) Example 7— Stratix® 10 SX (–1V, –2V, and –3V parts) Example 8— Stratix® 10 SX (–2L and –3X parts) Example 9— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 10— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 11— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 12— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 13— Stratix® 10 MX (–1V, –2V, and –3V parts) Example 14— Stratix® 10 MX (–1V, –2V, and –3V parts) Example 15— Stratix® 10 MX (E-Tile) Example 16— Stratix® 10 TX (–1V, –2V, and –3V parts) Example 17— Stratix® 10 TX (–2L and –3X parts) Example 18— Stratix® 10 DX (–1V, –2V, and –3V parts) Example 19— Stratix® 10 GX 10M Example 20— Stratix® 10 GX 10M
Stratix® 10 Device Family Pin Connection Guidelines

3 V Compatible I/O Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 4.  3 V Compatible I/Os Pins
Note: The I/O pins are tri-stated with a weak pull-up during power up.
Pin Name ( Stratix® 10 Devices) Pin Name ( Stratix® 10 GX 10M Device) Pin Functions Pin Description Connection Guidelines
IO3V[0,1,2,3,4,5,6,7]_[10,12,20,22] T[1,2,3,4]_IO3V[0,1,2,3,4,5,6,7] I/O

These are the 3.0 V I/O pins. Each H- or L- transceiver tile supports eight 3.0 V I/O pins. These pins support 1.2 V, 1.25 V, 1.35 V, 1.5 V, 1.8 V, 2.5 V, and 3.0 V I/O standards.

For details about the supported I/O standards, refer to the Stratix® 10 Device Datasheet .

Connect these pins according to the I/O interface standard you are using. You must provide power to the VCCR_GXB, VCCT_GXB, and VCCH_GXB pins of a transceiver tile to enable the 3.0 V I/O pins within that tile. For any transceiver tiles that have their VCCR_GXB, VCCT_GXB, and VCCH_GXB unpowered, the corresponding 3.0 V I/O pins within that tile is disabled.

Using 3 V I/O pins from an unpowered tile can potentially result in configuration failures.

Connect unused pins as defined in the Quartus® Prime software.

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