Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 8/26/2024
Public
Document Table of Contents
Document Table of Contents x
Stratix® 10 Device Family Pin Connection Guidelines
Stratix® 10 Device Family Pin Connection Guidelines x
Stratix® 10 Core Pins Stratix® 10 High Bandwidth Memory (HBM) Pins H-Tile and L-Tile Pins Stratix® 10 E-Tile Pins Stratix® 10 P-Tile Pins Stratix® 10 Hard Processor System (HPS) Pins Power Supply Sharing Guidelines for Stratix® 10 Devices Document Revision History for the Stratix® 10 Device Family Pin Connection Guidelines
Stratix® 10 Core Pins x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins 3 V Compatible I/O Pins 3.3 V I/O Pins Differential I/O Pins External Memory Interface Pins Voltage Sensor Pins Temperature Sensor Pins Reference Pins No Connect and DNU Pins Power Supply Pins Secure Device Manager (SDM) Pins Secure Device Manager (SDM) Optional Signal Pins Notes to Stratix® 10 Core Pins
Stratix® 10 High Bandwidth Memory (HBM) Pins x
UIB and eSRAM Pins Stratix® 10 HBM Power Supply Pins Notes to Stratix® 10 HBM Pins
H-Tile and L-Tile Pins x
H-Tile and L-Tile Pins
Stratix® 10 E-Tile Pins x
Stratix® 10 E-Tile Pins Notes to Stratix® 10 E-Tile Pins
Stratix® 10 P-Tile Pins x
Stratix® 10 P-Tile Power Supply Pins Stratix® 10 P-Tile Transceiver Pins
Stratix® 10 Hard Processor System (HPS) Pins x
HPS Supply Pins HPS Oscillator Clock Input Pin HPS JTAG Pins HPS GPIO Pins HPS SDMMC Pins HPS NAND Pins HPS USB Pins HPS EMAC Pins HPS I2C_EMAC and MDIO Pins HPS I2C Pins HPS SPI Pins HPS UART Pins HPS Trace Pins Notes to Stratix® 10 HPS Pins
Power Supply Sharing Guidelines for Stratix® 10 Devices x
Example 1— Stratix® 10 GX Example 2— Stratix® 10 GX Example 3— Stratix® 10 GX (only for the HF35 Package) Example 4— Stratix® 10 GX (only for the HF35 Package) Example 5— Stratix® 10 SX (–1V, –2V, and –3V parts) Example 6— Stratix® 10 SX (–2L and –3X parts) Example 7— Stratix® 10 SX (–1V, –2V, and –3V parts) Example 8— Stratix® 10 SX (–2L and –3X parts) Example 9— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 10— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 11— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) Example 12— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) Example 13— Stratix® 10 MX (–1V, –2V, and –3V parts) Example 14— Stratix® 10 MX (–1V, –2V, and –3V parts) Example 15— Stratix® 10 MX (E-Tile) Example 16— Stratix® 10 TX (–1V, –2V, and –3V parts) Example 17— Stratix® 10 TX (–2L and –3X parts) Example 18— Stratix® 10 DX (–1V, –2V, and –3V parts) Example 19— Stratix® 10 GX 10M Example 20— Stratix® 10 GX 10M
Stratix® 10 Device Family Pin Connection Guidelines

Stratix® 10 P-Tile Transceiver Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 21.   Stratix® 10 P-Tile Transceiver Pins
Pin Name Pin Functions Pin Description Connection Guidelines
IO_AUX_RREF[10, 11, 12, 20, 21, 22]_P Input Reference resistor for P-Tile transceivers.

Connect each IO_AUX_RREF pin to a 2.8 KΩ resistor (±1%) to GND.

In the PCB layout, the trace from this pin to the resistor needs to be routed such that it avoids any aggressor signals.

If this tile is unused, you must connect the 2.8 KΩ resistor between this pin and GND.

U[10, 11, 12, 20, 21, 22]_P_IO_RESREF_0 Input Transceiver reference resistor connection for PMA circuitry to provide termination for calibration.

Connect each pin to 169 Ω (±1%, 100 ppm/C) precision resistor to GND if the UltraPath Interconnect (UPI)/ PCIe* is 85 Ω impedance.

Place this resistor very close to the IO_RESREF pin. Avoid routing any noisy signals next to this reference resistor or its traces. Tie resistor to GND plane through a via placed very close to the reference resistor.

External reference resistor parasitic capacitance load must be less than 6.5 pF.
I_PIN_PERST_N[10, 11, 12, 20, 21, 22]_P Input PCI Express* ( PCIe* ) Platform reset pin.

In a PCI Express* ( PCIe* ) adapter card implementation, connect the PCIe* nPERST signal from the PCIe* edge connector to each P-Tile transceiver bank I_PIN_PERST_N input.

Use a level translator to fan out and change the 3.3 V open-drain nPERST signal from the PCIe* connector to the 1.8 V I_PIN_PERST_N input of each P-Tile transceiver that is used on the board.

Provide a 1.8 V pull-up resistor to the I_PIN_PERST_N input as the nPERST signal from the PCIe* connector is an open-drain signal. You must pull up the 3.3 V PCIe* nPERST signal on the adapter card.

For the UltraPath Interconnect (UPI) mode, contact Altera for guidance.

If the tile is unused, tie to GND.

GXP[L, R][10, 11, 12][A, B, C]_TX_CH[0:19][p,n] Output

Differential-based transmitter pins, specific to P-Tile transceivers on the left (L) side and right (R) side of the device.

These pins support NRZ encoding up to 16Gbps.

Connection guidelines for the PCIe* and UltraPath Interconnect (UPI) modes are as follow:

  • PCIe* mode—TX pins must be AC coupled. Capacitor values range from 176nF to 256nF per PCIe* Gen 4 specification.
  • UPI mode—TX pins must be DC coupled.

When these pins are not used, they can be floating.
GXP[L, R][10, 11, 12][A, B, C]_RX_CH[0:19][p,n] Input

Differential-based receiver pins, specific to P-Tile transceivers on the left (L) side and right (R) side of the device.

These pins support NRZ encoding up to 16 Gbps.

 When these pins are not used, they must be tied via a 1 kΩ pull-down resistor to GND.
REFCLK_GXP[L, R][10, 11, 12][A, B, C]_CH[0, 2][p,n] Input Standard PCIe* HCSL reference clock input pins, specific to P-Tile transceivers on the left (L) side and right (R) side of the device.

For the HCSL I/O standard, it only supports DC coupling. In the PCIe* configuration, DC-coupling is allowed on the REFCLK if the selected REFCLK I/O standard is the HCSL I/O standard.

Connect each unused REFCLK_GXP pin to GND plane directly on its own via. Do not share vias when connecting to GND.

You must connect a 100 MHz reference clock to both reference clock inputs for x16 and 4x4 modes. These reference clocks must be derived from the same clock source. A fan-out buffer can be used but must meet a ±300 ppm requirement. For 2x8 modes, you can connect both reference clock inputs to the same clock source or connect to two independent clock sources.

If the P-Tile is completely unused, tie both REFCLK inputs to GND.

Unused reference clock pins must be tied to 1 kΩ pull-down resistor to GND.

S_STRAP[10,11,12,20,21,22]_P Input Internal strap pins.

For PCIe* only system, connect to GND.

For UltraPath Interconnect (UPI) applications, connect the strap pins as follows:

  • For a two socket (2S) Intel® Xeon® system, connect to GND.
  • For a four socket (4S) Intel® Xeon® system, pull up through a 10 kΩ resistor to VCCCLK_GXP (1.8 V).

For the UltraPath Interconnect (UPI) mode, contact Intel® for guidance.

NODE_ID[0,1][10,11,12,20,21,22]_P Input Internal node ID pins.

For PCIe* only system, connect both ID pins to GND.

For UltraPath Interconnect (UPI) applications, connect these ID pins to the corresponding CPU ID of the UPI interface.

  • NODE_ID0 connects to CPU0.
  • NODE_ID1 connects to CPU1.

If the tile is unused, tie to GND.

For the UltraPath Interconnect (UPI) mode, contact Altera for guidance.

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