Stratix® 10 Device Family Pin Connection Guidelines

ID 683028
Date 12/19/2024
Public
Document Table of Contents

1.6.2. HPS Oscillator Clock Input Pin

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 23.  HPS Oscillator Clock Input PinYou must provide one input clock source to the HPS.
HPS Pin Function Pin Description and Connection Guidelines Pin Type Valid Assignments
HPS_OSC_CLK

Clock input pin that drives the main PLL.

Connect a single-ended clock source to this pin. The I/O standard of the clock source must be compatible with VCCIO_HPS. For more information, refer to the valid frequency range of the clock source in the Stratix® 10 Device Datasheet .

Input Select one of the 48 HPS dedicated I/O in Platform Designer HPS Component.