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1.1. Stratix® 10 Core Pins
1.2. Stratix® 10 High Bandwidth Memory (HBM) Pins
1.3. H-Tile and L-Tile Pins
1.4. Stratix® 10 E-Tile Pins
1.5. Stratix® 10 P-Tile Pins
1.6. Stratix® 10 Hard Processor System (HPS) Pins
1.7. Power Supply Sharing Guidelines for Stratix® 10 Devices
1.8. Document Revision History for the Stratix® 10 Device Family Pin Connection Guidelines
1.1.1. Clock and PLL Pins
1.1.2. Dedicated Configuration/JTAG Pins
1.1.3. Optional/Dual-Purpose Configuration Pins
1.1.4. 3 V Compatible I/O Pins
1.1.5. 3.3 V I/O Pins
1.1.6. Differential I/O Pins
1.1.7. External Memory Interface Pins
1.1.8. Voltage Sensor Pins
1.1.9. Temperature Sensor Pins
1.1.10. Reference Pins
1.1.11. No Connect and DNU Pins
1.1.12. Power Supply Pins
1.1.13. Secure Device Manager (SDM) Pins
1.1.14. Secure Device Manager (SDM) Optional Signal Pins
1.1.15. Notes to Stratix® 10 Core Pins
1.6.1. HPS Supply Pins
1.6.2. HPS Oscillator Clock Input Pin
1.6.3. HPS JTAG Pins
1.6.4. HPS GPIO Pins
1.6.5. HPS SDMMC Pins
1.6.6. HPS NAND Pins
1.6.7. HPS USB Pins
1.6.8. HPS EMAC Pins
1.6.9. HPS I2C_EMAC and MDIO Pins
1.6.10. HPS I2C Pins
1.6.11. HPS SPI Pins
1.6.12. HPS UART Pins
1.6.13. HPS Trace Pins
1.6.14. Notes to Stratix® 10 HPS Pins
1.7.1. Example 1— Stratix® 10 GX
1.7.2. Example 2— Stratix® 10 GX
1.7.3. Example 3— Stratix® 10 GX (only for the HF35 Package)
1.7.4. Example 4— Stratix® 10 GX (only for the HF35 Package)
1.7.5. Example 5— Stratix® 10 SX (–1V, –2V, and –3V parts)
1.7.6. Example 6— Stratix® 10 SX (–2L and –3X parts)
1.7.7. Example 7— Stratix® 10 SX (–1V, –2V, and –3V parts)
1.7.8. Example 8— Stratix® 10 SX (–2L and –3X parts)
1.7.9. Example 9— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package)
1.7.10. Example 10— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package)
1.7.11. Example 11— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package)
1.7.12. Example 12— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package)
1.7.13. Example 13— Stratix® 10 MX (–1V, –2V, and –3V parts)
1.7.14. Example 14— Stratix® 10 MX (–1V, –2V, and –3V parts)
1.7.15. Example 15— Stratix® 10 MX (E-Tile)
1.7.16. Example 16— Stratix® 10 TX (–1V, –2V, and –3V parts)
1.7.17. Example 17— Stratix® 10 TX (–2L and –3X parts)
1.7.18. Example 18— Stratix® 10 DX (–1V, –2V, and –3V parts)
1.7.19. Example 19— Stratix® 10 GX 10M
1.7.20. Example 20— Stratix® 10 GX 10M
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1.6.2. HPS Oscillator Clock Input Pin
Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
HPS Pin Function | Pin Description and Connection Guidelines | Pin Type | Valid Assignments |
---|---|---|---|
HPS_OSC_CLK | Clock input pin that drives the main PLL. Connect a single-ended clock source to this pin. The I/O standard of the clock source must be compatible with VCCIO_HPS. For more information, refer to the valid frequency range of the clock source in the Stratix® 10 Device Datasheet . |
Input | Select one of the 48 HPS dedicated I/O in Platform Designer HPS Component. |