Stratix® 10 Device Family Pin Connection Guidelines

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ID 683028
Date 12/19/2024
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Document Table of Contents
Document Table of Contents x
1. Stratix® 10 Device Family Pin Connection Guidelines
1. Stratix® 10 Device Family Pin Connection Guidelines x
1.1. Stratix® 10 Core Pins 1.2. Stratix® 10 High Bandwidth Memory (HBM) Pins 1.3. H-Tile and L-Tile Pins 1.4. Stratix® 10 E-Tile Pins 1.5. Stratix® 10 P-Tile Pins 1.6. Stratix® 10 Hard Processor System (HPS) Pins 1.7. Power Supply Sharing Guidelines for Stratix® 10 Devices 1.8. Document Revision History for the Stratix® 10 Device Family Pin Connection Guidelines
1.1. Stratix® 10 Core Pins x
1.1.1. Clock and PLL Pins 1.1.2. Dedicated Configuration/JTAG Pins 1.1.3. Optional/Dual-Purpose Configuration Pins 1.1.4. 3 V Compatible I/O Pins 1.1.5. 3.3 V I/O Pins 1.1.6. Differential I/O Pins 1.1.7. External Memory Interface Pins 1.1.8. Voltage Sensor Pins 1.1.9. Temperature Sensor Pins 1.1.10. Reference Pins 1.1.11. No Connect and DNU Pins 1.1.12. Power Supply Pins 1.1.13. Secure Device Manager (SDM) Pins 1.1.14. Secure Device Manager (SDM) Optional Signal Pins 1.1.15. Notes to Stratix® 10 Core Pins
1.2. Stratix® 10 High Bandwidth Memory (HBM) Pins x
1.2.1. UIB and eSRAM Pins 1.2.2. Stratix® 10 HBM Power Supply Pins 1.2.3. Notes to Stratix® 10 HBM Pins
1.3. H-Tile and L-Tile Pins x
1.3.1. H-Tile and L-Tile Pins
1.4. Stratix® 10 E-Tile Pins x
1.4.1. Stratix® 10 E-Tile Pins 1.4.2. Notes to Stratix® 10 E-Tile Pins
1.5. Stratix® 10 P-Tile Pins x
1.5.1. Stratix® 10 P-Tile Power Supply Pins 1.5.2. Stratix® 10 P-Tile Transceiver Pins
1.6. Stratix® 10 Hard Processor System (HPS) Pins x
1.6.1. HPS Supply Pins 1.6.2. HPS Oscillator Clock Input Pin 1.6.3. HPS JTAG Pins 1.6.4. HPS GPIO Pins 1.6.5. HPS SDMMC Pins 1.6.6. HPS NAND Pins 1.6.7. HPS USB Pins 1.6.8. HPS EMAC Pins 1.6.9. HPS I2C_EMAC and MDIO Pins 1.6.10. HPS I2C Pins 1.6.11. HPS SPI Pins 1.6.12. HPS UART Pins 1.6.13. HPS Trace Pins 1.6.14. Notes to Stratix® 10 HPS Pins
1.7. Power Supply Sharing Guidelines for Stratix® 10 Devices x
1.7.1. Example 1— Stratix® 10 GX 1.7.2. Example 2— Stratix® 10 GX 1.7.3. Example 3— Stratix® 10 GX (only for the HF35 Package) 1.7.4. Example 4— Stratix® 10 GX (only for the HF35 Package) 1.7.5. Example 5— Stratix® 10 SX (–1V, –2V, and –3V parts) 1.7.6. Example 6— Stratix® 10 SX (–2L and –3X parts) 1.7.7. Example 7— Stratix® 10 SX (–1V, –2V, and –3V parts) 1.7.8. Example 8— Stratix® 10 SX (–2L and –3X parts) 1.7.9. Example 9— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) 1.7.10. Example 10— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) 1.7.11. Example 11— Stratix® 10 SX (–1V, –2V, and –3V parts) (only for the HF35 Package) 1.7.12. Example 12— Stratix® 10 SX (–2L and –3X parts) (only for the HF35 Package) 1.7.13. Example 13— Stratix® 10 MX (–1V, –2V, and –3V parts) 1.7.14. Example 14— Stratix® 10 MX (–1V, –2V, and –3V parts) 1.7.15. Example 15— Stratix® 10 MX (E-Tile) 1.7.16. Example 16— Stratix® 10 TX (–1V, –2V, and –3V parts) 1.7.17. Example 17— Stratix® 10 TX (–2L and –3X parts) 1.7.18. Example 18— Stratix® 10 DX (–1V, –2V, and –3V parts) 1.7.19. Example 19— Stratix® 10 GX 10M 1.7.20. Example 20— Stratix® 10 GX 10M
1. Stratix® 10 Device Family Pin Connection Guidelines

1.1.12. Power Supply Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 12.  Power Supply Pins (See Notes 4 through 10)
Pin Name ( Stratix® 10 Devices) Pin Name ( Stratix® 10 GX 10M Device) Pin Functions Pin Description Connection Guidelines
VCCP VCCP Power VCCP supplies power to the periphery.

VCC and VCCP must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator.

For details about the recommended operating conditions, refer to the Electrical Characteristics in the Stratix® 10 Device Datasheet .

Use the Stratix® 10 Early Power Estimator (EPE) or Power Thermal Calculator (PTC), and the Quartus® Prime Power Analyzer to determine the current requirements for VCCP and other power supplies. Decoupling for these pins depends on the decoupling requirements of the specific board.

See Notes 2, 3, 4, 6, and 10 in the Notes to Stratix® 10 Core Pins section.

VCC VCC Power VCC supplies power to the core.

VCC and VCCP must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator.

For details about the recommended operating conditions, refer to Electrical Characteristics in the Stratix® 10 Device Datasheet .

Use the Stratix® 10 Early Power Estimator (EPE) or Power Thermal Calculator (PTC), and the Quartus® Prime Power Analyzer to determine the current requirements for VCC and other power supplies. Decoupling for these pins depends on the decoupling requirements of the specific board.

See Notes 2, 3, 4, 6, and 10 in the Notes to Stratix® 10 Core Pins section.

VCCPT VCCPT Power Power supply for the programmable power technology and I/O pre-drivers.

Connect VCCPT to a 1.8 V low noise switching regulator. You have the option to source the following from the same regulator as VCCPT:

  • VCCIO_SDM and VCCIO_HPS
  • VCCIO and VCCIO3V if these rails are using the same voltage level
  • VCCBAT if this rail is using the same voltage level and the design security key feature is not required
  • VCCH_GXB, VCCA_PLL, VCCPLL_SDM, VCCPLL_HPS, and VCCADC with proper isolation filtering

Provide a minimum decoupling of 1 uF for the VCCPT power rail near the VCCPT pin.

A floating voltage may be observed on VCCPT during device power-up and power-down sequencing due to VCCERAM, with the magnitude of the floating voltage being lower than VCCPT. This is the expected behavior and will neither cause any functional failure nor reliability concerns to the device provided that the power-up or power-down sequence is followed.

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Stratix® 10 Devices.

See Notes 2, 3, 4, 7, and 10 in the Notes to Stratix® 10 Core Pins section.

VCCA_PLL VCCA_PLL_F[1,2] Power PLL Analog power.

Connect VCCA_PLL to a 1.8 V low noise switching regulator. With proper isolation filtering, you have the option to source VCCA_PLL from the same regulator as VCCPT.

See Notes 2, 3, 4, 7, and 10 in the Notes to Stratix® 10 Core Pins section.

VCCIO([2][A,B,C,F,L,M,N], [3][A,B,C,I,J,K,L])

VCCIO2[A,B,C,F,G,H,I, J,K,L,M,N]_F[1,2]

VCCIO3[A,B,C,D,E,F,G,H,I,J,K,L]_F[1,2]

Power

These are the supply voltage pins for the I/O banks. Each bank can support a different voltage level.

Supported VCCIO standards include the following:

  • Diff HSTL/HSTL(12,15,18)
  • Diff SSTL/SSTL(12,125, 135, 15, 18)
  • Diff HSUL/HSUL(12)
  • Diff POD 12
  • LVDS/Mini_LVDS/RSDS
  • 1.2 V, 1.5 V, and 1.8 V

These VCCIO guidelines only apply to non-HF35 package devices and HF35 package devices with exception of the GX 400 (1SG040), SX 400 (1SX040), and TX 400 (1ST040) devices. If you are using the HF35 package of the GX 400 (1SG040), SX 400 (1SX040), and TX 400 (1ST040) devices, refer to the 3.3 V I/O Pins table in this document for the VCCIO3C and VCCIO3D connection guidelines.

Connect these pins to 1.2 V, 1.25 V, 1.35 V, 1. 5V, or 1.8 V supplies, depending on the I/O standard required by the specific bank.

You have the option to power down unused I/O banks by connecting their VCCIO pin to GND.

During the power-up sequence only, a transient current whose magnitude is less than the VCCIO operating static current may be observed as the VCCIO transistors become operational. This is the expected behavior and will neither cause any functional failure nor reliability concerns to the device provided that the power-up or power-down sequence is followed.

When I/O bank 3A is used for Avalon® streaming x16 or Avalon® streaming x32 configuration mode, you must connect the VCCIO3A power supply to the VCCIO_SDM power supply for proper device functionality.

For more details, refer to the Stratix® 10 General Purpose I/O User Guide.

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Stratix® 10 Devices.

See Notes 2, 3, 4, 8, and 10 in the Notes to Stratix® 10 Core Pins section.

VCCIO3V VCCIO3V_T[1,2,3,4] Power Power supply of the 3 V I/O bank.

Connect these pins to 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.0 V supplies, depending on the I/O standard required by the specified bank.

VCCIO3V must be powered on for proper device operation even if the VCCIO3V banks are unused.

VCCR_GXB, VCCT_GXB, and VCCH_GXB must be powered up to operate the VCCIO3V bank.

For more details, refer to the Stratix® 10 General Purpose I/O User Guide .

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Stratix® 10 Devices.

See Notes 2, 3, 4, 8, and 10 in the Notes to Stratix® 10 Core Pins section.

VCCIO_SDM VCCIO_SDM_F[1,2] Power Configuration pins power supply.

Connect these pins to a 1.8 V power supply. When dual-purpose configuration pins are used for configuration, tie VCCIO of the bank where the dual-purpose configuration pins reside to the same regulator as VCCIO_SDM.

When these pins require the same voltage level as VCCIO, you have the option to tie them to the same regulator as VCCIO.

Provide a minimum decoupling of 47 nF for the VCCIO_SDM power rail near the VCCIO_SDM pin.

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Stratix® 10 Devices.

See Notes 2, 3, 4, and 10 in the Notes to Stratix® 10 Core Pins section.

VCCERAM VCCERAM Power Embedded memory and digital transceiver power supply.

Connect all VCCERAM pins to a 0.9 V low noise switching power supply.

VCCPLLDIG_SDM must be sourced from the same regulator as VCCERAM with proper isolation filtering.

For more details, refer to the Stratix® 10 Device Datasheet .

See Notes 2, 3, 7, and 10 in the Notes to Stratix® 10 Core Pins section.

VCCPLLDIG_SDM VCCPLLDIG_SDM_F[1,2] Power SDM block PLL power pins. VCCPLLDIG_SDM must be sourced from the same regulator as VCCERAM with proper isolation filtering.
VCCBAT VCCBAT_F[1,2] Power Battery back-up power supply for design security volatile key register.

When using the design security volatile key, connect this pin to a non-volatile battery power source in the range of 1.2 V to 1.8 V.

When not using the volatile key, tie this pin to the 1.8-V VCCPT.

This pin must be properly powered as per the recommended voltage range as the power-on reset (POR) circuitry of the Stratix® 10 devices monitors VCCBAT.

Provide a minimum decoupling of 47 nF for the VCCBAT power rail near the VCCBAT pin.

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Stratix® 10 Devices.

VCCPLL_SDM VCCPLL_SDM_F[1,2] Power VCCPLL_SDM supplies analog power to the SDM block PLLs.

Connect these pins to a 1.8 V low noise power supply through a proper isolation filter.

With proper isolation filtering, you have the option to source VCCPLL_SDM from the same regulator as VCCPT when all power rails require 1.8 V.

Decoupling for these pins depends on the design decoupling requirements of the specific board.

See Notes 2, 3, 4, and 7 in the Notes to Stratix® 10 Core Pins section.

GND — Ground Device ground pins. Connect all GND pins to the board ground plane.
VREFB[[2][A,B,C,F,G,H,I,J,K,L,M,N], [3][A,B,C,D,E,F,G,H,I,J,K,L]]N0

VREFB2[A,B,C,F,G,H,I,J,K,L,M,N]N0_F[1,2]

VREFB3[A,B,C,D,E,F,G,H,I,J,K,L]N0_F[1,2]

Power Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then use these pins as voltage-reference pins for the bank.

If the VREF pins are not used, connect them to either VCCIO in the bank in which the pins reside or GND.

See Notes 2, 8, and 10 in the Notes to Stratix® 10 Core Pins section.

VCCLSENSE VCCLSENSE_F[1,2] Power Differential sense line to external regulator.

VCCLSENSE and GNDSENSE are differential remote sense pins for the VCC power. Connect your regulators' differential remote sense lines to the respective VCCLSENSE and GNDSENSE pins. This compensates for the DC IR drop associated with the PCB and device package from the VCC power. Route these connections as differential pair traces and keep them isolated from any other noise source.

You must connect the VCCLSENSE and GNDSENSE lines to the regulator's remote sense inputs.

GNDSENSE GNDSENSE_F[1,2] Power
VCCADC VCCADC_F[1,2] Power ADC power pin for the voltage sensors.

You must supply a low noise 1.8 V power supply to this pin if you are using the internal voltage sensors of the Stratix® 10 device.

When you are using the voltage sensors, tie this pin to VCCA_PLL with proper isolation filtering.

If you are not using the voltage sensors, tie this pin to VCCA_PLL.

VCCFUSEWR_SDM VCCFUSEWR_SDM_F[1,2] Power The required power supply to program (write) the optional, one-time programmable eFuses. These eFuses are an integral part of the Stratix® 10 security architecture. For more information, refer to the Stratix® 10 Device Security User Guide.

2.4 V power supply is required on this pin if field-programming of the eFuses is required. If field-programming of the eFuses is not required, tie this pin to VCCPT or leave it unconnected (floating). Do not tie this pin to GND.

If field-programming of the eFuses is required, Altera recommends you to use an adjustable regulator that is set to 2.4 V output when programming the eFuses and 1.8 V output at all other times.

A floating voltage may be observed on the VCCFUSEWR_SDM power during power-up and power-down sequencing due to VCCPT and/or VCCERAM, with the total magnitude of the floating voltage being lower than VCCFUSEWR_SDM.

During the power-up sequence only, a transient current whose magnitude is less than the VCCFUSEWR_SDM operating transient current may be observed. The floating voltage and transient current are expected behavior and will neither cause any functional failure nor reliability concerns to the device provided that the power-up or power-down sequence is followed.

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