Developer Guide

Intel oneAPI DPC++/C++ Compiler Handbook for Intel FPGAs

ID 785441
Date 5/08/2024
Public

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Document Table of Contents

Latency Control Properties (Beta)

The following table summarizes the latency control properties:

Latency Control Properties
Argument Description Example
sycl::ext::intel::experimental::latency_anchor_id<N> A label that you can associate with pipes and LSU functions
// The following write occurs exactly 2 cycles after the label-0 function, i.e.,
// the read above. Also, it has a label 1.
Pipe2::write(
  value,
  sycl::ext::oneapi::experimental::properties(
    sycl::ext::intel::experimental::latency_anchor_id<1>,
    sycl::ext::intel::experimental::latency_constraint<
      0, sycl::ext::intel::experimental::latency_control_type::exact,
      2>));
sycl::ext::intel::experimental::latency_constraint<A, B, C> A constraint that you can associate with pipes and LSU functions
NOTE:

Latency control APIs are provided on read() and write() member functions of the sycl::ext::intel::experimental::pipe class, and on load() and store() member functions of the sycl::ext::intel::experimental::lsu class. Other than the latency controls support, the experimental pipe and LSU are identical to sycl::ext::intel::pipe and sycl::ext::intel::lsu, and the <sycl/ext/intel/fpga_extensions.hpp> header file provides experimental pipe and LSU. These member functions (read(), write(), load(), and store()) can accept a property list instance (sycl::ext::oneapi::experimental::properties) as a function argument.

For detailed information about the variables, refer to Latency Controls (Beta).