Visible to Intel only — GUID: GUID-08E8772C-4909-4365-A607-5CD7439AA912
Visible to Intel only — GUID: GUID-08E8772C-4909-4365-A607-5CD7439AA912
Latency Control Properties (Beta)
The following table summarizes the latency control properties:
Argument | Description | Example |
---|---|---|
sycl::ext::intel::experimental::latency_anchor_id<N> | A label that you can associate with pipes and LSU functions |
|
sycl::ext::intel::experimental::latency_constraint<A, B, C> | A constraint that you can associate with pipes and LSU functions |
Latency control APIs are provided on read() and write() member functions of the sycl::ext::intel::experimental::pipe class, and on load() and store() member functions of the sycl::ext::intel::experimental::lsu class. Other than the latency controls support, the experimental pipe and LSU are identical to sycl::ext::intel::pipe and sycl::ext::intel::lsu, and the <sycl/ext/intel/fpga_extensions.hpp> header file provides experimental pipe and LSU. These member functions (read(), write(), load(), and store()) can accept a property list instance (sycl::ext::oneapi::experimental::properties) as a function argument.
For detailed information about the variables, refer to Latency Controls (Beta).