Visible to Intel only — GUID: GUID-360FD831-724A-441A-B0D7-3731433D7925
Visible to Intel only — GUID: GUID-360FD831-724A-441A-B0D7-3731433D7925
Evaluate Your Kernel Through Simulation
The Questa*-Intel® FPGA Edition and Questa*-Intel® FPGA Starter Edition software assess the functionality of your kernel.
The simulator flow generates a simulation binary file that runs on the host. The hardware portion of your code is evaluated in an RTL simulator, and the host portion is executed natively on the processor. This feature allows you to simulate the functionality of your kernel and iterate on your design without needing to compile your kernel to hardware and run on the FPGA each time.
Use the simulator when you want an insight into the dynamic performance of your kernel and more information about the functional correctness of your kernel than emulation or the reporting tools provide.
Verifying the functionality of your design in this way is sometimes called debugging through simulation.
To verify the design functionality from your design simulation, use the following debugging techniques:
Run the executable that the compiler generates by targeting the FPGA device.
Write variable values to output pipes or mm_host interfaces at certain points in your code.
Review the waveforms generated when running your design.
The compiler does not log signals by default when you compile your design. To enable signal logging in simulation, refer to Debug During Verification.
The simulator is cycle accurate and bit-accurate. It has a netlist identical to the generated hardware and can provide full waveforms for debugging. View the waveforms with Siemens* EDA (formerly Mentor Graphics) Questa* software.