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Intel oneAPI DPC++/C++ Compiler Handbook for Intel FPGAs
Introduction To FPGA Design Concepts
Intel oneAPI FPGA Development
Getting Started with the Intel oneAPI DPC++/C++ Compiler for Intel FPGA Development
Defining a Kernel for FPGAs
Debugging and Verifying Your Design
Analyzing Your Design
Optimizing Your Kernel
Optimizing Your Host Application
Integrating Your Kernel into DSP Builder for Intel FPGAs
Integrating Your RTL IP Core Into a System
RTL IP Core Kernel Interfaces
Loops
Pipes
Data Types and Arithmetic Operations
Parallelism
Memories and Memory Operations
Libraries
Additional FPGA Acceleration Flow Considerations
Additional SYCL* HLS Flow Considerations
FPGA Optimization Flags, Attributes, Pragmas, and Extensions
Quick Reference
Additional Information
Document Revision History for the Intel oneAPI DPC++/C++ Compiler Handbook for Intel FPGAs
Notices and Disclaimers
Set the Environment Variables and Launch Visual Studio* Code
Create an FPGA Visual Studio* Code Project
Enable Code Completion in a Visual Studio* Code Project
Configure Running and Debugging in a Visual Studio* Code Project
Debugging Your Kernel in Visual Studio* Code with a Native Debugger
Generate and View the FPGA Optimization Report
Build and Run the FPGA Hardware Image
Throughput
Resource Use
System-level Profiling Using the Intercept Layer for OpenCL™ Applications
Multi-Threaded Host Application
Utilizing Hardware Kernel Invocation Queue
Double Buffering Host Utilizing Kernel Invocation Queue
N-Way Buffering to Overlap Kernel Execution
Prepinning Memory
Simple Host-Device Streaming
Buffered Host-Device Streaming
Refactor the Loop-Carried Data Dependency
Relax Loop-Carried Dependency
Transfer Loop-Carried Dependency to Local Memory
Minimize the Memory Dependencies for Loop Pipelining
Unroll Loops
Fuse Loops to Reduce Overhead and Improve Performance
Optimize Loops With Loop Speculation
Remove Loop Bottlenecks
Improve fMAX/II with Shannonization
Optimize Inner Loop Throughput
Improve Loop Performance by Caching Data in On-Chip Memory
Global Memory Bandwidth Use Calculation
Manual Partition of Global Memory
Partitioning Buffers Across Different Memory Types (Heterogeneous Memory)
Partitioning Buffers Across Memory Channels of the Same Memory Type
Ignoring Dependencies Between Accessor Arguments
Contiguous Memory Accesses
Static Memory Coalescing
Specify Schedule fMAX Target for Kernels (-Xsclock=<clock target>)
Create a 2xclock Interface (-Xsuse-2xclock)
Disable Burst-Interleaving of Global Memory (-Xsno-interleaving=<global_memory_name>)
Force Ring Interconnect for Global Memory (-Xsglobal-ring)
Force a Single Store Ring to Reduce Area (-Xsforce-single-store-ring)
Force Fewer Read Data Reorder Units to Reduce Area (-Xsnum-reorder)
Disable Hardware Kernel Invocation Queue (-Xsno-hardware-kernel-invocation-queue)
Modify the Handshaking Protocol Between Clusters (-Xshyper-optimized-handshaking)
Disable Automatic Fusion of Loops (-Xsdisable-auto-loop-fusion)
Fuse Adjacent Loops With Unequal Trip Counts (-Xsenable-unequal-tc-fusion)
Pipeline Loops in Non-task Kernels (-Xsauto-pipeline)
Control Semantics of Floating-Point Operations (-fp-model=<value>)
Modify the Rounding Mode of Floating-point Operations (-Xsrounding=<rounding_type>)
Global Control of Exit FIFO Latency of Stall-free Clusters (-Xssfc-exit-fifo-type=<value>)
Enable the Read-Only Cache for Read-Only Accessors (-Xsread-only-cache-size=<N>)
Control Hardware Implementation of the Supported Data Types and Math Operations (-Xsdsp-mode=<option>)
Generate Register Map Wrapper (-Xsregister-map-wrapper-type)
Allow Wide Memory Initialization (-Xsallow-wide-mif)
Visible to Intel only — GUID: GUID-859B1157-86B5-4BF4-881E-6F1C90566233
Modify the Handshaking Protocol Between Clusters (-Xshyper-optimized-handshaking)
To modify the handshaking protocol between clusters, use the -Xshyper-optimized-handshaking=<auto|off|on> option in your icpx command. The -Xshyper-optimized-handshaking option can be set to one of the following values:
- auto: The Intel® oneAPI DPC++/C++ Compiler chooses whether to enable or disable the optimization. This is the default behavior for all flows except the minimum latency optimization flow.
- on: The compiler enables the optimization if possible. Use this value to achieve a higher fMAX. When you enable the optimization, the compiler adds pipeline registers to the handshaking paths of the stallable nodes. As a result, you observe higher fMAX at the cost of increased area and latency.
- off: The compiler attempts to optimize for lower latency at the potential cost of lower fMAX. Disabling hyper-optimized handshaking might also decrease area. This is useful for smaller designs where you are willing to give up fMAX for lower latency and area. This is the default for the minimum latency optimization flow.
Examples
icpx -fsycl -fintelfpga -Xshardware -Xshyper-optimized-handshaking=auto <source_file>.cpp
icpx -fsycl -fintelfpga -Xshardware -Xshyper-optimized-handshaking=off <source_file>.cpp
icpx -fsycl -fintelfpga -Xshardware -Xshyper-optimized-handshaking=on <source_file>.cpp
NOTE:
The -Xshyper-optimized-handshaking option applies only to designs targeting Agilex™ 7 and Stratix® 10 devices. If you use this option on other target devices, the compiler fails and produces an error. This option applies only when running the report or hardware flow.
Parent topic: Optimization Flags